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restricted debugging to 3.9 only

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This commit is contained in:
Josy Boelen 2021-03-07 11:06:26 +01:00
parent 48f7a5897c
commit 19066e0656
3 changed files with 5 additions and 5 deletions
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2
myhdl/conversion/_analyze.py
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@ -682,7 +682,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
elif v == 1:
node.edge = sig.posedge
if sys.version_info >= (3, 8, 0):
if sys.version_info >= (3, 9, 0):
def visit_Constant(self, node):
node.obj = None # safeguarding?

4
myhdl/conversion/_toVHDL.py
View File

@ -1192,7 +1192,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
self.visit(right)
self.write(suf)
if sys.version_info >= (3, 8, 0):
if sys.version_info >= (3, 9, 0):
def visit_Constant(self, node):
if isinstance(node.value, int):
@ -2291,7 +2291,7 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
right.vhd = vhd_signed(right.vhd.size + 1)
node.vhdOri = copy(node.vhd)
if sys.version_info >= (3, 8, 0):
if sys.version_info >= (3, 9, 0):
def visit_Constant(self, node):
if isinstance(node.value, int):

4
myhdl/conversion/_toVerilog.py
View File

@ -1133,7 +1133,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
elif isinstance(obj, int):
s = self.IntRepr(obj)
elif isinstance(obj, tuple): # Python3.9+ ast.Index serves a tuple
print(obj)
print('toVerilog', addSignBit, n, obj)
s = n
# # print(ast.dump(ast.parse('l[i]', mode='eval')))
# # Expression(body=Subscript(value=Name(id='l', ctx=Load()), slice=Index(value=Name(id='i', ctx=Load())), ctx=Load()))
@ -1647,7 +1647,7 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
return
self.generic_visit(node)
if sys.version_info >= (3, 8, 0):
if sys.version_info >= (3, 9, 0):
def visit_Constant(self, node):
node.signed = False