added run_all.py

example/manual/bin2gray.py

@@ -28,7 +28,11 @@ def testBench(width):
 
     return (dut, stimulus())
 
-if __name__ == '__main__':
+def main():
     Simulation(testBench(width=3)).run()
     
 
+if __name__ == '__main__':
+    main()
+    
+

example/manual/fifo.py

@@ -1,5 +1,6 @@
 from __future__ import generators
 import sys
+import traceback
 
 from myhdl import Signal, Simulation, posedge, negedge, delay, \
                   StopSimulation, join
@@ -124,6 +125,13 @@ def test():
     
 sim = Simulation(clkGen(), test(), dut)
     
-if __name__ == "__main__":
-    sim.run()
+def main():
+    try:
+        sim.run()
+    except:
+        traceback.print_exc()
     
+if __name__ == '__main__':
+    main()
+           
+ 

example/manual/greetings.py

@@ -27,6 +27,10 @@ def greetings():
 
     return clkGen1, clkGen2, sayHello1, sayHello2
 
-sim = Simulation(greetings())
-sim.run(50)
+def main():
+    sim = Simulation(greetings())
+    sim.run(50)
+
+if __name__ == '__main__':
+    main()
 

example/manual/hec.py

@@ -23,7 +23,9 @@ headers = ( 0x00000000,
             0xbac6f4ca
           )
 
-if __name__ == '__main__':
+def main():
     for header in headers:
         print hex(calculateHec(intbv(header)))
         
+if __name__ == '__main__':
+    main()

example/manual/hello1.py

@@ -6,6 +6,11 @@ def sayHello():
         yield delay(10)
         print "%s Hello World!" % now()
 
-sim = Simulation(sayHello())
-sim.run(30)
+def main():
+    sim = Simulation(sayHello())
+    sim.run(30)
+
+if __name__ == '__main__':
+    main()
+
 

example/manual/hello2.py

@@ -15,6 +15,9 @@ def sayHello():
         yield posedge(clk)
         print "%s Hello World!" % now()
 
-sim = Simulation(clkGen(), sayHello())
-sim.run(50)
+def main():
+    sim = Simulation(clkGen(), sayHello())
+    sim.run(50)
 
+if __name__ == '__main__':
+    main()

example/manual/inc.py

@@ -52,10 +52,14 @@ def monitor():
         print "   %s      %s" % (enable, count)
         
 
-if __name__ == "__main__":
+def main():
     Simulation(clockGen(), stimulus(), INC_1, monitor(), INC_1).run()
     
 
+if __name__ == '__main__':
+    main()
+           
+           
     
         
     

example/manual/mux.py

@@ -28,6 +28,8 @@ def test():
         yield delay(10)
         print "%s %s %s %s" % (z, a, b, sel)
 
-if __name__ == "__main__":
+def main():
     Simulation(MUX_1, test()).run()    
     
+if __name__ == '__main__':
+    main()

example/manual/rs232.py

@@ -107,14 +107,17 @@ def testJoin():
         txData = intbv(val)
         yield join(rs232_rx(rx, rxData), rs232_tx(tx, txData, duration=T_10200))
     
+def main():
+    print "\n\n## stimulus ##\n"
+    Simulation(stimulus()).run()
+    print "\n\n## test ##\n" 
+    Simulation(test()).run()
+    print "\n\n## testTimeout ##\n"
+    Simulation(testTimeout()).run()
+    print "\n\n## testNoJoin ##\n"
+    Simulation(testNoJoin()).run()
+    print "\n\n## testJoin ##\n"
+    Simulation(testJoin()).run()
 
-print "\n\n## stimulus ##\n"
-Simulation(stimulus()).run()
-print "\n\n## test ##\n" 
-Simulation(test()).run()
-print "\n\n## testTimeout ##\n"
-Simulation(testTimeout()).run()
-print "\n\n## testNoJoin ##\n"
-Simulation(testNoJoin()).run()
-print "\n\n## testJoin ##\n"
-Simulation(testJoin()).run()
+if __name__ == '__main__':
+    main()

example/manual/sparseMemory.py

@@ -1,5 +1,7 @@
 from __future__ import generators
 
+import traceback
+
 from myhdl import Signal, Simulation, posedge, negedge, delay, StopSimulation
 
 
@@ -99,10 +101,14 @@ def test():
 
 sim = Simulation(clkGen(), test(), dut)
     
-if __name__ == "__main__":
-    sim.run()
-    
+def main():
+    try:
+        sim.run()
+    except:
+        traceback.print_exc()
     
+if __name__ == '__main__':
+    main()