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221
myhdl/test/toVHDL/test_fsm.py
Normal file
221
myhdl/test/toVHDL/test_fsm.py
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@ -0,0 +1,221 @@
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import os
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path = os.path
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from myhdl import *
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from myhdl.test import verifyConversion
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# SEARCH, CONFIRM, SYNC = range(3)
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ACTIVE_LOW = bool(0)
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FRAME_SIZE = 8
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t_State_b = enum('SEARCH', 'CONFIRM', 'SYNC')
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t_State_oh = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot")
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t_State_oc = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_cold")
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def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
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""" Framing control FSM.
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SOF -- start-of-frame output bit
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state -- FramerState output
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syncFlag -- sync pattern found indication input
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clk -- clock input
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reset_n -- active low reset
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"""
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index = Signal(intbv(0)[8:]) # position in frame
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@always(clk.posedge, reset_n.negedge)
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def FSM():
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if reset_n == ACTIVE_LOW:
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SOF.next = 0
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index.next = 0
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state.next = t_State.SEARCH
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else:
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index.next = (index + 1) % FRAME_SIZE
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SOF.next = 0
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if state == t_State.SEARCH:
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index.next = 1
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if syncFlag:
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state.next = t_State.CONFIRM
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elif state == t_State.CONFIRM:
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if index == 0:
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if syncFlag:
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state.next = t_State.SYNC
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else:
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state.next = t_State.SEARCH
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elif state == t_State.SYNC:
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if index == 0:
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if not syncFlag:
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state.next = t_State.SEARCH
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SOF.next = (index == FRAME_SIZE-1)
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else:
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raise ValueError("Undefined state")
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return FSM
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def FramerCtrl_alt(SOF, state, syncFlag, clk, reset_n, t_State):
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""" Framing control FSM.
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SOF -- start-of-frame output bit
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state -- FramerState output
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syncFlag -- sync pattern found indication input
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clk -- clock input
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reset_n -- active low reset
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"""
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def FSM():
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index = intbv(0)[8:] # position in frame
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state_var = t_State.SEARCH
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while True:
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yield clk.posedge, reset_n.negedge
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if reset_n == ACTIVE_LOW:
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SOF.next = 0
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index[:] = 0
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state_var = t_State.SEARCH
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state.next = t_State.SEARCH
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else:
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SOF_var = 0
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if state == t_State.SEARCH:
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index[:] = 0
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if syncFlag:
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state_var = t_State.CONFIRM
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elif state == t_State.CONFIRM:
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if index == 0:
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if syncFlag:
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state_var = t_State.SYNC
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else:
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state_var = t_State.SEARCH
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elif state == t_State.SYNC:
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if index == 0:
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if not syncFlag:
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state_var = t_State.SEARCH
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SOF_var = (index == FRAME_SIZE-1)
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else:
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raise ValueError("Undefined state")
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index[:]= (index + 1) % FRAME_SIZE
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SOF.next = SOF_var
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state.next = state_var
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FSM_1 = FSM()
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return FSM_1
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def FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State):
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""" Framing control FSM.
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SOF -- start-of-frame output bit
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state -- FramerState output
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syncFlag -- sync pattern found indication input
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clk -- clock input
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reset_n -- active low reset
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"""
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index = intbv(0, min=0, max=8) # position in frame
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while 1:
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yield clk.posedge, reset_n.negedge
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if reset_n == ACTIVE_LOW:
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SOF.next = 0
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index[:] = 0
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state.next = t_State.SEARCH
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else:
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SOF.next = 0
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if state == t_State.SEARCH:
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index[:] = 0
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if syncFlag:
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state.next = t_State.CONFIRM
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elif state == t_State.CONFIRM:
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if index == 0:
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if syncFlag:
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state.next = t_State.SYNC
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else:
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state.next = t_State.SEARCH
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elif state == t_State.SYNC:
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if index == 0:
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if not syncFlag:
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state.next = t_State.SEARCH
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SOF.next = (index == FRAME_SIZE-1)
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else:
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raise ValueError("Undefined state")
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index[:]= (index + 1) % FRAME_SIZE
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def FSMBench(FramerCtrl, t_State):
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SOF = Signal(bool(0))
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SOF_v = Signal(bool(0))
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syncFlag = Signal(bool(0))
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clk = Signal(bool(0))
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reset_n = Signal(bool(1))
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state = Signal(t_State.SEARCH)
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state_v = Signal(intbv(0)[8:])
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framerctrl_inst = FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State)
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def clkgen():
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clk.next = 0
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reset_n.next = 1
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yield delay(10)
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reset_n.next = 0
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yield delay(10)
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reset_n.next = 1
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yield delay(10)
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for i in range(1000):
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yield delay(10)
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clk.next = not clk
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table = (12, 8, 8, 4, 11, 8, 8, 7, 6, 8, 8)
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def stimulus():
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for i in range(3):
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yield clk.posedge
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for i in range(len(table)):
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n = table[i]
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syncFlag.next = 1
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yield clk.posedge
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syncFlag.next = 0
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for i in range(n-1):
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yield clk.posedge
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raise StopSimulation
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def check():
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while True:
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yield clk.negedge
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print state
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# print clk
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# print state
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# print "MyHDL: %s %s" % (SOF, hex(state))
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# print "Verilog: %s %s" % (SOF_v, hex(state_v))
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return framerctrl_inst, clkgen(), stimulus(), check()
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verifyConversion(FSMBench, FramerCtrl, t_State_b)
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## def testRef(self):
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## for t_State in (t_State_b, t_State_oc, t_State_oh):
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## tb_fsm = self.bench(FramerCtrl_ref, t_State)
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## sim = Simulation(tb_fsm)
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## sim.run()
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## def testAlt(self):
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## for t_State in (t_State_b, t_State_oc, t_State_oh):
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## tb_fsm = self.bench(FramerCtrl_alt, t_State)
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## sim = Simulation(tb_fsm)
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## sim.run()
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## def testDoc(self):
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## tb_fsm = self.bench(FramerCtrl, t_State_oh)
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## sim = Simulation(tb_fsm)
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## sim.run()
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149
myhdl/test/toVHDL/test_inc.py
Normal file
149
myhdl/test/toVHDL/test_inc.py
Normal file
@ -0,0 +1,149 @@
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import sys
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import os
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path = os.path
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import unittest
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from unittest import TestCase
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import random
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from random import randrange
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random.seed(2)
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from myhdl import *
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from myhdl.test import verifyConversion
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ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1)
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def incRef(count, enable, clock, reset, n):
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""" Incrementer with enable.
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count -- output
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enable -- control input, increment when 1
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clock -- clock input
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reset -- asynchronous reset input
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n -- counter max value
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"""
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while 1:
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yield clock.posedge, reset.negedge
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if reset == ACTIVE_LOW:
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count.next = 0
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else:
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if enable:
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count.next = (count + 1) % n
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def inc(count, enable, clock, reset, n):
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""" Incrementer with enable.
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count -- output
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enable -- control input, increment when 1
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clock -- clock input
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reset -- asynchronous reset input
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n -- counter max value
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"""
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@always(clock.posedge, reset.negedge)
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def incProcess():
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if reset == ACTIVE_LOW:
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count.next = 0
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else:
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if enable:
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count.next = (count + 1) % n
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return incProcess
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def inc2(count, enable, clock, reset, n):
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@always(clock.posedge, reset.negedge)
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def incProcess():
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if reset == ACTIVE_LOW:
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count.next = 0
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else:
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if enable:
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if count == n-1:
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count.next = 0
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else:
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count.next = count + 1
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return incProcess
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def incTask(count, enable, clock, reset, n):
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def incTaskFunc(cnt, enable, reset, n):
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if enable:
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cnt[:] = (cnt + 1) % n
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@instance
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def incTaskGen():
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cnt = intbv(0)[8:]
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while 1:
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yield clock.posedge, reset.negedge
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if reset == ACTIVE_LOW:
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cnt[:] = 0
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count.next = 0
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else:
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# print count
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incTaskFunc(cnt, enable, reset, n)
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count.next = cnt
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return incTaskGen
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def incTaskFreeVar(count, enable, clock, reset, n):
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def incTaskFunc():
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if enable:
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count.next = (count + 1) % n
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@always(clock.posedge, reset.negedge)
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def incTaskGen():
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if reset == ACTIVE_LOW:
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count.next = 0
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else:
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# print count
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incTaskFunc()
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return incTaskGen
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def tb_inc():
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NR_CYCLES = 200
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m = 8
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n = 2 ** m
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count = Signal(intbv(0)[m:])
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count_v = Signal(intbv(0)[m:])
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enable = Signal(bool(0))
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clock, reset = [Signal(bool(0)) for i in range(2)]
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inc_inst = inc(count, enable, clock, reset, n=n)
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@instance
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def clockgen():
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clock.next = 0
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for i in range(NR_CYCLES):
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yield delay(10)
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clock.next = not clock
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@instance
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def monitor():
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reset.next = 0
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enable.next = 1
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yield clock.negedge
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reset.next = 1
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yield clock.negedge
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while True:
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yield clock.negedge
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print count
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return inc_inst, clockgen, monitor
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verifyConversion(tb_inc)
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503
myhdl/test/toVHDL/test_ops.py
Normal file
503
myhdl/test/toVHDL/test_ops.py
Normal file
@ -0,0 +1,503 @@
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import os
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path = os.path
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import random
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from random import randrange
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random.seed(2)
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from myhdl import *
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from myhdl.test import verifyConversion
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def binaryOps(
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Bitand,
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Bitor,
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Bitxor,
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FloorDiv,
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LeftShift,
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Modulo,
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Mul,
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Pow,
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RightShift,
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Sub,
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Sum,
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EQ,
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NE,
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LT,
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GT,
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LE,
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GE,
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Booland,
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Boolor,
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left, right):
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while 1:
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yield left, right
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## Bitand.next = left & right
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## Bitor.next = left | right
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## Bitxor.next = left ^ right
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## if right != 0:
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## FloorDiv.next = left // right
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## if left < 256 and right < 40:
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## LeftShift.next = left << right
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## if right != 0:
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## Modulo.next = left % right
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## Mul.next = left * right
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# Icarus doesn't support ** yet
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#if left < 256 and right < 40:
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# Pow.next = left ** right
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## Pow.next = 0
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## RightShift.next = left >> right
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if left >= right:
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Sub.next = left - right
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Sum.next = left + right
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EQ.next = left == right
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NE.next = left != right
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LT.next = left < right
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GT.next = left > right
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LE.next = left <= right
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GE.next = left >= right
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## Booland.next = bool(left) and bool(right)
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## Boolor.next = bool(left) or bool(right)
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def binaryBench(m, n):
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M = 2**m
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N = 2**n
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P = min(M, N)
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left = Signal(intbv(0)[m:])
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right = Signal(intbv(0)[n:])
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Bitand = Signal(intbv(0)[max(m, n):])
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Bitor = Signal(intbv(0)[max(m, n):])
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Bitxor = Signal(intbv(0)[max(m, n):])
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FloorDiv = Signal(intbv(0)[m:])
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LeftShift = Signal(intbv(0)[64:])
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Modulo = Signal(intbv(0)[m:])
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Mul = Signal(intbv(0)[m+n:])
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Pow = Signal(intbv(0)[64:])
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RightShift = Signal(intbv(0)[m:])
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Sub = Signal(intbv(0)[max(m, n):])
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Sum = Signal(intbv(0)[max(m, n)+1:])
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EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)]
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Booland, Boolor = [Signal(bool()) for i in range(2)]
|
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binops = binaryOps(Bitand,
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Bitor,
|
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Bitxor,
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FloorDiv,
|
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LeftShift,
|
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Modulo,
|
||||
Mul,
|
||||
Pow,
|
||||
RightShift,
|
||||
Sub,
|
||||
Sum,
|
||||
EQ,
|
||||
NE,
|
||||
LT,
|
||||
GT,
|
||||
LE,
|
||||
GE,
|
||||
Booland,
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||||
Boolor,
|
||||
left, right)
|
||||
|
||||
def stimulus():
|
||||
## for i in range(P):
|
||||
## print i
|
||||
## left.next = intbv(i)
|
||||
## right.next = intbv(i)
|
||||
## yield delay(10)
|
||||
## for i in range(100):
|
||||
## left.next = randrange(M)
|
||||
## right.next = randrange(N)
|
||||
## yield delay(10)
|
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left.next = 1
|
||||
right.next = 1
|
||||
yield delay(10)
|
||||
left.next = 0
|
||||
right.next = 0
|
||||
yield delay(10)
|
||||
left.next = 0
|
||||
right.next = N-1
|
||||
yield delay(10)
|
||||
left.next = M-1
|
||||
right.next = 0
|
||||
yield delay(10)
|
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left.next = M-1
|
||||
right.next = N-1
|
||||
# raise StopSimulation
|
||||
|
||||
|
||||
def check():
|
||||
while True:
|
||||
yield left, right
|
||||
yield delay(1)
|
||||
# print "%s %s %s %s" % (left, right, Boolor, Boolor_v)
|
||||
## self.assertEqual(Bitand, Bitand_v)
|
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## self.assertEqual(Bitor, Bitor_v)
|
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## self.assertEqual(Bitxor, Bitxor_v)
|
||||
## self.assertEqual(FloorDiv, FloorDiv_v)
|
||||
## self.assertEqual(LeftShift, LeftShift_v)
|
||||
## self.assertEqual(Modulo, Modulo_v)
|
||||
## self.assertEqual(Mul, Mul_v)
|
||||
## # self.assertEqual(Pow, Pow_v)
|
||||
## self.assertEqual(RightShift, RightShift_v)
|
||||
## self.assertEqual(Sub, Sub_v)
|
||||
## self.assertEqual(Sum, Sum_v)
|
||||
print Sum
|
||||
## self.assertEqual(EQ, EQ_v)
|
||||
## self.assertEqual(NE, NE_v)
|
||||
## self.assertEqual(LT, LT_v)
|
||||
## self.assertEqual(GT, GT_v)
|
||||
## self.assertEqual(LE, LE_v)
|
||||
## self.assertEqual(GE, GE_v)
|
||||
## self.assertEqual(Booland, Booland_v)
|
||||
## self.assertEqual(Boolor, Boolor_v)
|
||||
|
||||
return binops, stimulus(), check()
|
||||
|
||||
|
||||
for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
|
||||
verifyConversion(binaryBench, m, n)
|
||||
|
||||
|
||||
|
||||
## def multiOps(
|
||||
## Bitand,
|
||||
## Bitor,
|
||||
## Bitxor,
|
||||
## Booland,
|
||||
## Boolor,
|
||||
## argm, argn, argp):
|
||||
## while 1:
|
||||
## yield argm, argn, argp
|
||||
## Bitand.next = argm & argn & argp
|
||||
## Bitor.next = argm | argn | argp
|
||||
## Bitxor.next = argm ^ argn ^ argp
|
||||
## Booland.next = bool(argm) and bool(argn) and bool(argp)
|
||||
## Boolor.next = bool(argm) and bool(argn) and bool(argp)
|
||||
|
||||
|
||||
## def multiOps_v( name,
|
||||
## Bitand,
|
||||
## Bitor,
|
||||
## Bitxor,
|
||||
## Booland,
|
||||
## Boolor,
|
||||
## argm, argn, argp):
|
||||
|
||||
## return setupCosimulation(**locals())
|
||||
|
||||
## class TestMultiOps(TestCase):
|
||||
|
||||
## def multiBench(self, m, n, p):
|
||||
|
||||
## M = 2**m
|
||||
## N = 2**n
|
||||
## P = 2**p
|
||||
|
||||
## argm = Signal(intbv(0)[m:])
|
||||
## argn = Signal(intbv(0)[n:])
|
||||
## argp = Signal(intbv(0)[p:])
|
||||
## Bitand = Signal(intbv(0)[max(m, n, p):])
|
||||
## Bitand_v = Signal(intbv(0)[max(m, n, p):])
|
||||
## Bitor = Signal(intbv(0)[max(m, n, p):])
|
||||
## Bitor_v = Signal(intbv(0)[max(m, n, p):])
|
||||
## Bitxor = Signal(intbv(0)[max(m, n, p):])
|
||||
## Bitxor_v = Signal(intbv(0)[max(m, n, p):])
|
||||
## Booland, Boolor = [Signal(bool()) for i in range(2)]
|
||||
## Booland_v, Boolor_v, = [Signal(bool()) for i in range(2)]
|
||||
|
||||
## multiops = toVerilog(multiOps,
|
||||
## Bitand,
|
||||
## Bitor,
|
||||
## Bitxor,
|
||||
## Booland,
|
||||
## Boolor,
|
||||
## argm, argn, argp)
|
||||
## multiops_v = multiOps_v(multiOps.func_name,
|
||||
## Bitand_v,
|
||||
## Bitor_v,
|
||||
## Bitxor_v,
|
||||
## Booland_v,
|
||||
## Boolor_v,
|
||||
## argm, argn, argp)
|
||||
|
||||
## def stimulus():
|
||||
## for i in range(min(M, N, P)):
|
||||
## # print i
|
||||
## argm.next = intbv(i)
|
||||
## argn.next = intbv(i)
|
||||
## argp.next = intbv(i)
|
||||
## yield delay(10)
|
||||
## for i in range(100):
|
||||
## argm.next = randrange(M)
|
||||
## argn.next = randrange(N)
|
||||
## argp.next = randrange(P)
|
||||
## yield delay(10)
|
||||
## for j, k, l in ((0, 0, 0), (0, 0, P-1), (0, N-1, P-1),
|
||||
## (M-1, 0, 0), (M-1, 0, P-1), (M-1, N-1, 0),
|
||||
## (0, N-1, 0), (M-1, N-1, P-1)):
|
||||
## argm.next = j
|
||||
## argn.next = k
|
||||
## argp.next = l
|
||||
## yield delay(10)
|
||||
|
||||
## def check():
|
||||
## while 1:
|
||||
## yield argm, argn, argp
|
||||
## yield delay(1)
|
||||
## # print "%s %s %s %s %s" % (argm, argn, argp, Bitxor, Bitxor_v)
|
||||
## self.assertEqual(Bitand, Bitand_v)
|
||||
## self.assertEqual(Bitor, Bitor_v)
|
||||
## self.assertEqual(Bitxor, Bitxor_v)
|
||||
## self.assertEqual(Booland, Booland_v)
|
||||
## self.assertEqual(Boolor, Boolor_v)
|
||||
|
||||
## return multiops, multiops_v, stimulus(), check()
|
||||
|
||||
|
||||
## def testMultiOps(self):
|
||||
## for m, n, p in ((4, 4, 4,), (5, 3, 2), (3, 4, 6), (3, 7, 4)):
|
||||
## sim = self.multiBench(m, n, p)
|
||||
## Simulation(sim).run()
|
||||
|
||||
|
||||
|
||||
## def unaryOps(
|
||||
## Not,
|
||||
## Invert,
|
||||
## UnaryAdd,
|
||||
## UnarySub,
|
||||
## arg):
|
||||
## while 1:
|
||||
## yield arg
|
||||
## Not.next = not arg
|
||||
## Invert.next = ~arg
|
||||
## UnaryAdd.next = +arg
|
||||
## UnarySub.next = --arg
|
||||
|
||||
## def unaryOps_v(name,
|
||||
## Not,
|
||||
## Invert,
|
||||
## UnaryAdd,
|
||||
## UnarySub,
|
||||
## arg):
|
||||
## return setupCosimulation(**locals())
|
||||
|
||||
|
||||
|
||||
## class TestUnaryOps(TestCase):
|
||||
|
||||
## def unaryBench(self, m):
|
||||
|
||||
## M = 2**m
|
||||
|
||||
## arg = Signal(intbv(0)[m:])
|
||||
## Not = Signal(bool(0))
|
||||
## Not_v = Signal(bool(0))
|
||||
## Invert = Signal(intbv(0)[m:])
|
||||
## Invert_v = Signal(intbv(0)[m:])
|
||||
## UnaryAdd = Signal(intbv(0)[m:])
|
||||
## UnaryAdd_v = Signal(intbv(0)[m:])
|
||||
## UnarySub = Signal(intbv(0)[m:])
|
||||
## UnarySub_v = Signal(intbv(0)[m:])
|
||||
|
||||
## unaryops = toVerilog(unaryOps,
|
||||
## Not,
|
||||
## Invert,
|
||||
## UnaryAdd,
|
||||
## UnarySub,
|
||||
## arg)
|
||||
## unaryops_v = unaryOps_v(unaryOps.func_name,
|
||||
## Not_v,
|
||||
## Invert_v,
|
||||
## UnaryAdd_v,
|
||||
## UnarySub_v,
|
||||
## arg)
|
||||
|
||||
## def stimulus():
|
||||
## for i in range(M):
|
||||
## arg.next = intbv(i)
|
||||
## yield delay(10)
|
||||
## for i in range(100):
|
||||
## arg.next = randrange(M)
|
||||
## yield delay(10)
|
||||
## raise StopSimulation
|
||||
|
||||
## def check():
|
||||
## while 1:
|
||||
## yield arg
|
||||
## yield delay(1)
|
||||
## self.assertEqual(Not, Not_v)
|
||||
## self.assertEqual(Invert, Invert_v)
|
||||
## self.assertEqual(UnaryAdd, UnaryAdd_v)
|
||||
## self.assertEqual(UnarySub, UnarySub_v)
|
||||
|
||||
## return unaryops, unaryops_v, stimulus(), check()
|
||||
|
||||
## def testUnaryOps(self):
|
||||
## for m in (4, 7):
|
||||
## sim = self.unaryBench(m)
|
||||
## Simulation(sim).run()
|
||||
|
||||
|
||||
## def augmOps(
|
||||
## Bitand,
|
||||
## Bitor,
|
||||
## Bitxor,
|
||||
## FloorDiv,
|
||||
## LeftShift,
|
||||
## Modulo,
|
||||
## Mul,
|
||||
## RightShift,
|
||||
## Sub,
|
||||
## Sum,
|
||||
## left, right):
|
||||
## var = intbv(0)[max(64, len(left) + len(right)):]
|
||||
## while 1:
|
||||
## yield left, right
|
||||
## var[:] = left
|
||||
## var &= right
|
||||
## Bitand.next = var
|
||||
## var[:] = left
|
||||
## var |= right
|
||||
## Bitor.next = var
|
||||
## var[:] = left
|
||||
## var ^= left
|
||||
## Bitxor.next = var
|
||||
## if right != 0:
|
||||
## var[:] = left
|
||||
## var //= right
|
||||
## FloorDiv.next = var
|
||||
## if left < 256 and right < 40:
|
||||
## var[:] = left
|
||||
## var <<= right
|
||||
## LeftShift.next = var
|
||||
## if right != 0:
|
||||
## var[:] = left
|
||||
## var %= right
|
||||
## Modulo.next = var
|
||||
## var[:] = left
|
||||
## var *= right
|
||||
## Mul.next = var
|
||||
## var[:] = left
|
||||
## var >>= right
|
||||
## RightShift.next = var
|
||||
## if left >= right:
|
||||
## var[:] = left
|
||||
## var -= right
|
||||
## Sub.next = var
|
||||
## var[:] = left
|
||||
## var += right
|
||||
## Sum.next = var
|
||||
|
||||
|
||||
## def augmOps_v( name,
|
||||
## Bitand,
|
||||
## Bitor,
|
||||
## Bitxor,
|
||||
## FloorDiv,
|
||||
## LeftShift,
|
||||
## Modulo,
|
||||
## Mul,
|
||||
## RightShift,
|
||||
## Sub,
|
||||
## Sum,
|
||||
## left, right):
|
||||
## return setupCosimulation(**locals())
|
||||
|
||||
## class TestAugmOps(TestCase):
|
||||
|
||||
## def augmBench(self, m, n):
|
||||
|
||||
## M = 2**m
|
||||
## N = 2**n
|
||||
|
||||
## left = Signal(intbv(0)[m:])
|
||||
## right = Signal(intbv(0)[n:])
|
||||
## Bitand = Signal(intbv(0)[max(m, n):])
|
||||
## Bitand_v = Signal(intbv(0)[max(m, n):])
|
||||
## Bitor = Signal(intbv(0)[max(m, n):])
|
||||
## Bitor_v = Signal(intbv(0)[max(m, n):])
|
||||
## Bitxor = Signal(intbv(0)[max(m, n):])
|
||||
## Bitxor_v = Signal(intbv(0)[max(m, n):])
|
||||
## FloorDiv = Signal(intbv(0)[m:])
|
||||
## FloorDiv_v = Signal(intbv(0)[m:])
|
||||
## LeftShift = Signal(intbv(0)[64:])
|
||||
## LeftShift_v = Signal(intbv(0)[64:])
|
||||
## Modulo = Signal(intbv(0)[m:])
|
||||
## Modulo_v = Signal(intbv(0)[m:])
|
||||
## Mul = Signal(intbv(0)[m+n:])
|
||||
## Mul_v = Signal(intbv(0)[m+n:])
|
||||
## RightShift = Signal(intbv(0)[m:])
|
||||
## RightShift_v = Signal(intbv(0)[m:])
|
||||
## Sub = Signal(intbv(0)[max(m, n):])
|
||||
## Sub_v = Signal(intbv(0)[max(m, n):])
|
||||
## Sum = Signal(intbv(0)[max(m, n)+1:])
|
||||
## Sum_v = Signal(intbv(0)[max(m, n)+1:])
|
||||
|
||||
## augmops = toVerilog(augmOps,
|
||||
## Bitand,
|
||||
## Bitor,
|
||||
## Bitxor,
|
||||
## FloorDiv,
|
||||
## LeftShift,
|
||||
## Modulo,
|
||||
## Mul,
|
||||
## RightShift,
|
||||
## Sub,
|
||||
## Sum,
|
||||
## left, right)
|
||||
## augmops_v = augmOps_v( augmOps.func_name,
|
||||
## Bitand_v,
|
||||
## Bitor_v,
|
||||
## Bitxor_v,
|
||||
## FloorDiv_v,
|
||||
## LeftShift_v,
|
||||
## Modulo_v,
|
||||
## Mul_v,
|
||||
## RightShift_v,
|
||||
## Sub_v,
|
||||
## Sum_v,
|
||||
## left, right)
|
||||
|
||||
## def stimulus():
|
||||
## for i in range(min(M, N)):
|
||||
## # print i
|
||||
## left.next = intbv(i)
|
||||
## right.next = intbv(i)
|
||||
## yield delay(10)
|
||||
## for i in range(100):
|
||||
## left.next = randrange(M)
|
||||
## right.next = randrange(N)
|
||||
## yield delay(10)
|
||||
## for j, k in ((0, 0), (0, N-1), (M-1, 0), (M-1, N-1)):
|
||||
## left.next = j
|
||||
## right.next = k
|
||||
## yield delay(10)
|
||||
|
||||
## def check():
|
||||
## while 1:
|
||||
## yield left, right
|
||||
## yield delay(1)
|
||||
## # print "%s %s %s %s" % (left, right, Boolor, Boolor_v)
|
||||
## self.assertEqual(Bitand, Bitand_v)
|
||||
## self.assertEqual(Bitor, Bitor_v)
|
||||
## self.assertEqual(Bitxor, Bitxor_v)
|
||||
## self.assertEqual(FloorDiv, FloorDiv_v)
|
||||
## self.assertEqual(LeftShift, LeftShift_v)
|
||||
## self.assertEqual(Modulo, Modulo_v)
|
||||
## self.assertEqual(Mul, Mul_v)
|
||||
## self.assertEqual(RightShift, RightShift_v)
|
||||
## self.assertEqual(Sub, Sub_v)
|
||||
## self.assertEqual(Sum, Sum_v)
|
||||
|
||||
## return augmops, augmops_v, stimulus(), check()
|
||||
|
||||
|
||||
## def testAugmOps(self):
|
||||
## for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
|
||||
## sim = self.augmBench(m, n)
|
||||
## Simulation(sim).run()
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user