From 1aa24190e08517b6eb458ab7522a889f39094a7f Mon Sep 17 00:00:00 2001 From: jand Date: Mon, 14 Aug 2006 21:52:10 +0000 Subject: [PATCH] added --- myhdl/test/toVHDL/test_fsm.py | 221 +++++++++++++++ myhdl/test/toVHDL/test_inc.py | 149 ++++++++++ myhdl/test/toVHDL/test_ops.py | 503 ++++++++++++++++++++++++++++++++++ 3 files changed, 873 insertions(+) create mode 100644 myhdl/test/toVHDL/test_fsm.py create mode 100644 myhdl/test/toVHDL/test_inc.py create mode 100644 myhdl/test/toVHDL/test_ops.py diff --git a/myhdl/test/toVHDL/test_fsm.py b/myhdl/test/toVHDL/test_fsm.py new file mode 100644 index 00000000..e752097d --- /dev/null +++ b/myhdl/test/toVHDL/test_fsm.py @@ -0,0 +1,221 @@ +import os +path = os.path + +from myhdl import * +from myhdl.test import verifyConversion + +# SEARCH, CONFIRM, SYNC = range(3) +ACTIVE_LOW = bool(0) +FRAME_SIZE = 8 +t_State_b = enum('SEARCH', 'CONFIRM', 'SYNC') +t_State_oh = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot") +t_State_oc = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_cold") + +def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State): + + """ Framing control FSM. + + SOF -- start-of-frame output bit + state -- FramerState output + syncFlag -- sync pattern found indication input + clk -- clock input + reset_n -- active low reset + + """ + + index = Signal(intbv(0)[8:]) # position in frame + + @always(clk.posedge, reset_n.negedge) + def FSM(): + if reset_n == ACTIVE_LOW: + SOF.next = 0 + index.next = 0 + state.next = t_State.SEARCH + else: + index.next = (index + 1) % FRAME_SIZE + SOF.next = 0 + if state == t_State.SEARCH: + index.next = 1 + if syncFlag: + state.next = t_State.CONFIRM + elif state == t_State.CONFIRM: + if index == 0: + if syncFlag: + state.next = t_State.SYNC + else: + state.next = t_State.SEARCH + elif state == t_State.SYNC: + if index == 0: + if not syncFlag: + state.next = t_State.SEARCH + SOF.next = (index == FRAME_SIZE-1) + else: + raise ValueError("Undefined state") + + return FSM + + +def FramerCtrl_alt(SOF, state, syncFlag, clk, reset_n, t_State): + + """ Framing control FSM. + + SOF -- start-of-frame output bit + state -- FramerState output + syncFlag -- sync pattern found indication input + clk -- clock input + reset_n -- active low reset + + """ + + + def FSM(): + index = intbv(0)[8:] # position in frame + state_var = t_State.SEARCH + while True: + yield clk.posedge, reset_n.negedge + if reset_n == ACTIVE_LOW: + SOF.next = 0 + index[:] = 0 + state_var = t_State.SEARCH + state.next = t_State.SEARCH + else: + SOF_var = 0 + if state == t_State.SEARCH: + index[:] = 0 + if syncFlag: + state_var = t_State.CONFIRM + elif state == t_State.CONFIRM: + if index == 0: + if syncFlag: + state_var = t_State.SYNC + else: + state_var = t_State.SEARCH + elif state == t_State.SYNC: + if index == 0: + if not syncFlag: + state_var = t_State.SEARCH + SOF_var = (index == FRAME_SIZE-1) + else: + raise ValueError("Undefined state") + index[:]= (index + 1) % FRAME_SIZE + SOF.next = SOF_var + state.next = state_var + + FSM_1 = FSM() + return FSM_1 + + +def FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State): + + """ Framing control FSM. + + SOF -- start-of-frame output bit + state -- FramerState output + syncFlag -- sync pattern found indication input + clk -- clock input + reset_n -- active low reset + + """ + + index = intbv(0, min=0, max=8) # position in frame + while 1: + yield clk.posedge, reset_n.negedge + if reset_n == ACTIVE_LOW: + SOF.next = 0 + index[:] = 0 + state.next = t_State.SEARCH + else: + SOF.next = 0 + if state == t_State.SEARCH: + index[:] = 0 + if syncFlag: + state.next = t_State.CONFIRM + elif state == t_State.CONFIRM: + if index == 0: + if syncFlag: + state.next = t_State.SYNC + else: + state.next = t_State.SEARCH + elif state == t_State.SYNC: + if index == 0: + if not syncFlag: + state.next = t_State.SEARCH + SOF.next = (index == FRAME_SIZE-1) + else: + raise ValueError("Undefined state") + index[:]= (index + 1) % FRAME_SIZE + + + + +def FSMBench(FramerCtrl, t_State): + + SOF = Signal(bool(0)) + SOF_v = Signal(bool(0)) + syncFlag = Signal(bool(0)) + clk = Signal(bool(0)) + reset_n = Signal(bool(1)) + state = Signal(t_State.SEARCH) + state_v = Signal(intbv(0)[8:]) + + framerctrl_inst = FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State) + + def clkgen(): + clk.next = 0 + reset_n.next = 1 + yield delay(10) + reset_n.next = 0 + yield delay(10) + reset_n.next = 1 + yield delay(10) + for i in range(1000): + yield delay(10) + clk.next = not clk + + table = (12, 8, 8, 4, 11, 8, 8, 7, 6, 8, 8) + + def stimulus(): + for i in range(3): + yield clk.posedge + for i in range(len(table)): + n = table[i] + syncFlag.next = 1 + yield clk.posedge + syncFlag.next = 0 + for i in range(n-1): + yield clk.posedge + raise StopSimulation + + def check(): + while True: + yield clk.negedge + print state + # print clk +# print state + # print "MyHDL: %s %s" % (SOF, hex(state)) + # print "Verilog: %s %s" % (SOF_v, hex(state_v)) + + return framerctrl_inst, clkgen(), stimulus(), check() + + +verifyConversion(FSMBench, FramerCtrl, t_State_b) + +## def testRef(self): +## for t_State in (t_State_b, t_State_oc, t_State_oh): +## tb_fsm = self.bench(FramerCtrl_ref, t_State) +## sim = Simulation(tb_fsm) +## sim.run() + + + +## def testAlt(self): +## for t_State in (t_State_b, t_State_oc, t_State_oh): +## tb_fsm = self.bench(FramerCtrl_alt, t_State) +## sim = Simulation(tb_fsm) +## sim.run() + +## def testDoc(self): +## tb_fsm = self.bench(FramerCtrl, t_State_oh) +## sim = Simulation(tb_fsm) +## sim.run() + diff --git a/myhdl/test/toVHDL/test_inc.py b/myhdl/test/toVHDL/test_inc.py new file mode 100644 index 00000000..91fa1552 --- /dev/null +++ b/myhdl/test/toVHDL/test_inc.py @@ -0,0 +1,149 @@ +import sys +import os +path = os.path +import unittest +from unittest import TestCase +import random +from random import randrange +random.seed(2) + +from myhdl import * +from myhdl.test import verifyConversion + + +ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1) + +def incRef(count, enable, clock, reset, n): + """ Incrementer with enable. + + count -- output + enable -- control input, increment when 1 + clock -- clock input + reset -- asynchronous reset input + n -- counter max value + """ + while 1: + yield clock.posedge, reset.negedge + if reset == ACTIVE_LOW: + count.next = 0 + else: + if enable: + count.next = (count + 1) % n + +def inc(count, enable, clock, reset, n): + + """ Incrementer with enable. + + count -- output + enable -- control input, increment when 1 + clock -- clock input + reset -- asynchronous reset input + n -- counter max value + + """ + + @always(clock.posedge, reset.negedge) + def incProcess(): + if reset == ACTIVE_LOW: + count.next = 0 + else: + if enable: + count.next = (count + 1) % n + + return incProcess + +def inc2(count, enable, clock, reset, n): + + @always(clock.posedge, reset.negedge) + def incProcess(): + if reset == ACTIVE_LOW: + count.next = 0 + else: + if enable: + if count == n-1: + count.next = 0 + else: + count.next = count + 1 + return incProcess + + +def incTask(count, enable, clock, reset, n): + + def incTaskFunc(cnt, enable, reset, n): + if enable: + cnt[:] = (cnt + 1) % n + + @instance + def incTaskGen(): + cnt = intbv(0)[8:] + while 1: + yield clock.posedge, reset.negedge + if reset == ACTIVE_LOW: + cnt[:] = 0 + count.next = 0 + else: + # print count + incTaskFunc(cnt, enable, reset, n) + count.next = cnt + + return incTaskGen + + +def incTaskFreeVar(count, enable, clock, reset, n): + + def incTaskFunc(): + if enable: + count.next = (count + 1) % n + + @always(clock.posedge, reset.negedge) + def incTaskGen(): + if reset == ACTIVE_LOW: + count.next = 0 + else: + # print count + incTaskFunc() + + return incTaskGen + + +def tb_inc(): + + NR_CYCLES = 200 + + m = 8 + n = 2 ** m + + count = Signal(intbv(0)[m:]) + count_v = Signal(intbv(0)[m:]) + enable = Signal(bool(0)) + clock, reset = [Signal(bool(0)) for i in range(2)] + + + inc_inst = inc(count, enable, clock, reset, n=n) + + @instance + def clockgen(): + clock.next = 0 + for i in range(NR_CYCLES): + yield delay(10) + clock.next = not clock + + @instance + def monitor(): + reset.next = 0 + enable.next = 1 + yield clock.negedge + reset.next = 1 + yield clock.negedge + while True: + yield clock.negedge + print count + + return inc_inst, clockgen, monitor + + + +verifyConversion(tb_inc) + + + diff --git a/myhdl/test/toVHDL/test_ops.py b/myhdl/test/toVHDL/test_ops.py new file mode 100644 index 00000000..d7443196 --- /dev/null +++ b/myhdl/test/toVHDL/test_ops.py @@ -0,0 +1,503 @@ +import os +path = os.path +import random +from random import randrange +random.seed(2) + +from myhdl import * +from myhdl.test import verifyConversion + +def binaryOps( + Bitand, + Bitor, + Bitxor, + FloorDiv, + LeftShift, + Modulo, + Mul, + Pow, + RightShift, + Sub, + Sum, + EQ, + NE, + LT, + GT, + LE, + GE, + Booland, + Boolor, + left, right): + while 1: + yield left, right +## Bitand.next = left & right +## Bitor.next = left | right +## Bitxor.next = left ^ right +## if right != 0: +## FloorDiv.next = left // right +## if left < 256 and right < 40: +## LeftShift.next = left << right +## if right != 0: +## Modulo.next = left % right +## Mul.next = left * right + # Icarus doesn't support ** yet + #if left < 256 and right < 40: + # Pow.next = left ** right +## Pow.next = 0 +## RightShift.next = left >> right + if left >= right: + Sub.next = left - right + Sum.next = left + right + EQ.next = left == right + NE.next = left != right + LT.next = left < right + GT.next = left > right + LE.next = left <= right + GE.next = left >= right +## Booland.next = bool(left) and bool(right) +## Boolor.next = bool(left) or bool(right) + + +def binaryBench(m, n): + + M = 2**m + N = 2**n + P = min(M, N) + + left = Signal(intbv(0)[m:]) + right = Signal(intbv(0)[n:]) + Bitand = Signal(intbv(0)[max(m, n):]) + Bitor = Signal(intbv(0)[max(m, n):]) + Bitxor = Signal(intbv(0)[max(m, n):]) + FloorDiv = Signal(intbv(0)[m:]) + LeftShift = Signal(intbv(0)[64:]) + Modulo = Signal(intbv(0)[m:]) + Mul = Signal(intbv(0)[m+n:]) + Pow = Signal(intbv(0)[64:]) + RightShift = Signal(intbv(0)[m:]) + Sub = Signal(intbv(0)[max(m, n):]) + Sum = Signal(intbv(0)[max(m, n)+1:]) + EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)] + Booland, Boolor = [Signal(bool()) for i in range(2)] + + binops = binaryOps(Bitand, + Bitor, + Bitxor, + FloorDiv, + LeftShift, + Modulo, + Mul, + Pow, + RightShift, + Sub, + Sum, + EQ, + NE, + LT, + GT, + LE, + GE, + Booland, + Boolor, + left, right) + + def stimulus(): +## for i in range(P): +## print i +## left.next = intbv(i) +## right.next = intbv(i) +## yield delay(10) +## for i in range(100): +## left.next = randrange(M) +## right.next = randrange(N) +## yield delay(10) + left.next = 1 + right.next = 1 + yield delay(10) + left.next = 0 + right.next = 0 + yield delay(10) + left.next = 0 + right.next = N-1 + yield delay(10) + left.next = M-1 + right.next = 0 + yield delay(10) + left.next = M-1 + right.next = N-1 + # raise StopSimulation + + + def check(): + while True: + yield left, right + yield delay(1) + # print "%s %s %s %s" % (left, right, Boolor, Boolor_v) +## self.assertEqual(Bitand, Bitand_v) +## self.assertEqual(Bitor, Bitor_v) +## self.assertEqual(Bitxor, Bitxor_v) +## self.assertEqual(FloorDiv, FloorDiv_v) +## self.assertEqual(LeftShift, LeftShift_v) +## self.assertEqual(Modulo, Modulo_v) +## self.assertEqual(Mul, Mul_v) +## # self.assertEqual(Pow, Pow_v) +## self.assertEqual(RightShift, RightShift_v) +## self.assertEqual(Sub, Sub_v) +## self.assertEqual(Sum, Sum_v) + print Sum +## self.assertEqual(EQ, EQ_v) +## self.assertEqual(NE, NE_v) +## self.assertEqual(LT, LT_v) +## self.assertEqual(GT, GT_v) +## self.assertEqual(LE, LE_v) +## self.assertEqual(GE, GE_v) +## self.assertEqual(Booland, Booland_v) +## self.assertEqual(Boolor, Boolor_v) + + return binops, stimulus(), check() + + +for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)): + verifyConversion(binaryBench, m, n) + + + +## def multiOps( +## Bitand, +## Bitor, +## Bitxor, +## Booland, +## Boolor, +## argm, argn, argp): +## while 1: +## yield argm, argn, argp +## Bitand.next = argm & argn & argp +## Bitor.next = argm | argn | argp +## Bitxor.next = argm ^ argn ^ argp +## Booland.next = bool(argm) and bool(argn) and bool(argp) +## Boolor.next = bool(argm) and bool(argn) and bool(argp) + + +## def multiOps_v( name, +## Bitand, +## Bitor, +## Bitxor, +## Booland, +## Boolor, +## argm, argn, argp): + +## return setupCosimulation(**locals()) + +## class TestMultiOps(TestCase): + +## def multiBench(self, m, n, p): + +## M = 2**m +## N = 2**n +## P = 2**p + +## argm = Signal(intbv(0)[m:]) +## argn = Signal(intbv(0)[n:]) +## argp = Signal(intbv(0)[p:]) +## Bitand = Signal(intbv(0)[max(m, n, p):]) +## Bitand_v = Signal(intbv(0)[max(m, n, p):]) +## Bitor = Signal(intbv(0)[max(m, n, p):]) +## Bitor_v = Signal(intbv(0)[max(m, n, p):]) +## Bitxor = Signal(intbv(0)[max(m, n, p):]) +## Bitxor_v = Signal(intbv(0)[max(m, n, p):]) +## Booland, Boolor = [Signal(bool()) for i in range(2)] +## Booland_v, Boolor_v, = [Signal(bool()) for i in range(2)] + +## multiops = toVerilog(multiOps, +## Bitand, +## Bitor, +## Bitxor, +## Booland, +## Boolor, +## argm, argn, argp) +## multiops_v = multiOps_v(multiOps.func_name, +## Bitand_v, +## Bitor_v, +## Bitxor_v, +## Booland_v, +## Boolor_v, +## argm, argn, argp) + +## def stimulus(): +## for i in range(min(M, N, P)): +## # print i +## argm.next = intbv(i) +## argn.next = intbv(i) +## argp.next = intbv(i) +## yield delay(10) +## for i in range(100): +## argm.next = randrange(M) +## argn.next = randrange(N) +## argp.next = randrange(P) +## yield delay(10) +## for j, k, l in ((0, 0, 0), (0, 0, P-1), (0, N-1, P-1), +## (M-1, 0, 0), (M-1, 0, P-1), (M-1, N-1, 0), +## (0, N-1, 0), (M-1, N-1, P-1)): +## argm.next = j +## argn.next = k +## argp.next = l +## yield delay(10) + +## def check(): +## while 1: +## yield argm, argn, argp +## yield delay(1) +## # print "%s %s %s %s %s" % (argm, argn, argp, Bitxor, Bitxor_v) +## self.assertEqual(Bitand, Bitand_v) +## self.assertEqual(Bitor, Bitor_v) +## self.assertEqual(Bitxor, Bitxor_v) +## self.assertEqual(Booland, Booland_v) +## self.assertEqual(Boolor, Boolor_v) + +## return multiops, multiops_v, stimulus(), check() + + +## def testMultiOps(self): +## for m, n, p in ((4, 4, 4,), (5, 3, 2), (3, 4, 6), (3, 7, 4)): +## sim = self.multiBench(m, n, p) +## Simulation(sim).run() + + + +## def unaryOps( +## Not, +## Invert, +## UnaryAdd, +## UnarySub, +## arg): +## while 1: +## yield arg +## Not.next = not arg +## Invert.next = ~arg +## UnaryAdd.next = +arg +## UnarySub.next = --arg + +## def unaryOps_v(name, +## Not, +## Invert, +## UnaryAdd, +## UnarySub, +## arg): +## return setupCosimulation(**locals()) + + + +## class TestUnaryOps(TestCase): + +## def unaryBench(self, m): + +## M = 2**m + +## arg = Signal(intbv(0)[m:]) +## Not = Signal(bool(0)) +## Not_v = Signal(bool(0)) +## Invert = Signal(intbv(0)[m:]) +## Invert_v = Signal(intbv(0)[m:]) +## UnaryAdd = Signal(intbv(0)[m:]) +## UnaryAdd_v = Signal(intbv(0)[m:]) +## UnarySub = Signal(intbv(0)[m:]) +## UnarySub_v = Signal(intbv(0)[m:]) + +## unaryops = toVerilog(unaryOps, +## Not, +## Invert, +## UnaryAdd, +## UnarySub, +## arg) +## unaryops_v = unaryOps_v(unaryOps.func_name, +## Not_v, +## Invert_v, +## UnaryAdd_v, +## UnarySub_v, +## arg) + +## def stimulus(): +## for i in range(M): +## arg.next = intbv(i) +## yield delay(10) +## for i in range(100): +## arg.next = randrange(M) +## yield delay(10) +## raise StopSimulation + +## def check(): +## while 1: +## yield arg +## yield delay(1) +## self.assertEqual(Not, Not_v) +## self.assertEqual(Invert, Invert_v) +## self.assertEqual(UnaryAdd, UnaryAdd_v) +## self.assertEqual(UnarySub, UnarySub_v) + +## return unaryops, unaryops_v, stimulus(), check() + +## def testUnaryOps(self): +## for m in (4, 7): +## sim = self.unaryBench(m) +## Simulation(sim).run() + + +## def augmOps( +## Bitand, +## Bitor, +## Bitxor, +## FloorDiv, +## LeftShift, +## Modulo, +## Mul, +## RightShift, +## Sub, +## Sum, +## left, right): +## var = intbv(0)[max(64, len(left) + len(right)):] +## while 1: +## yield left, right +## var[:] = left +## var &= right +## Bitand.next = var +## var[:] = left +## var |= right +## Bitor.next = var +## var[:] = left +## var ^= left +## Bitxor.next = var +## if right != 0: +## var[:] = left +## var //= right +## FloorDiv.next = var +## if left < 256 and right < 40: +## var[:] = left +## var <<= right +## LeftShift.next = var +## if right != 0: +## var[:] = left +## var %= right +## Modulo.next = var +## var[:] = left +## var *= right +## Mul.next = var +## var[:] = left +## var >>= right +## RightShift.next = var +## if left >= right: +## var[:] = left +## var -= right +## Sub.next = var +## var[:] = left +## var += right +## Sum.next = var + + +## def augmOps_v( name, +## Bitand, +## Bitor, +## Bitxor, +## FloorDiv, +## LeftShift, +## Modulo, +## Mul, +## RightShift, +## Sub, +## Sum, +## left, right): +## return setupCosimulation(**locals()) + +## class TestAugmOps(TestCase): + +## def augmBench(self, m, n): + +## M = 2**m +## N = 2**n + +## left = Signal(intbv(0)[m:]) +## right = Signal(intbv(0)[n:]) +## Bitand = Signal(intbv(0)[max(m, n):]) +## Bitand_v = Signal(intbv(0)[max(m, n):]) +## Bitor = Signal(intbv(0)[max(m, n):]) +## Bitor_v = Signal(intbv(0)[max(m, n):]) +## Bitxor = Signal(intbv(0)[max(m, n):]) +## Bitxor_v = Signal(intbv(0)[max(m, n):]) +## FloorDiv = Signal(intbv(0)[m:]) +## FloorDiv_v = Signal(intbv(0)[m:]) +## LeftShift = Signal(intbv(0)[64:]) +## LeftShift_v = Signal(intbv(0)[64:]) +## Modulo = Signal(intbv(0)[m:]) +## Modulo_v = Signal(intbv(0)[m:]) +## Mul = Signal(intbv(0)[m+n:]) +## Mul_v = Signal(intbv(0)[m+n:]) +## RightShift = Signal(intbv(0)[m:]) +## RightShift_v = Signal(intbv(0)[m:]) +## Sub = Signal(intbv(0)[max(m, n):]) +## Sub_v = Signal(intbv(0)[max(m, n):]) +## Sum = Signal(intbv(0)[max(m, n)+1:]) +## Sum_v = Signal(intbv(0)[max(m, n)+1:]) + +## augmops = toVerilog(augmOps, +## Bitand, +## Bitor, +## Bitxor, +## FloorDiv, +## LeftShift, +## Modulo, +## Mul, +## RightShift, +## Sub, +## Sum, +## left, right) +## augmops_v = augmOps_v( augmOps.func_name, +## Bitand_v, +## Bitor_v, +## Bitxor_v, +## FloorDiv_v, +## LeftShift_v, +## Modulo_v, +## Mul_v, +## RightShift_v, +## Sub_v, +## Sum_v, +## left, right) + +## def stimulus(): +## for i in range(min(M, N)): +## # print i +## left.next = intbv(i) +## right.next = intbv(i) +## yield delay(10) +## for i in range(100): +## left.next = randrange(M) +## right.next = randrange(N) +## yield delay(10) +## for j, k in ((0, 0), (0, N-1), (M-1, 0), (M-1, N-1)): +## left.next = j +## right.next = k +## yield delay(10) + +## def check(): +## while 1: +## yield left, right +## yield delay(1) +## # print "%s %s %s %s" % (left, right, Boolor, Boolor_v) +## self.assertEqual(Bitand, Bitand_v) +## self.assertEqual(Bitor, Bitor_v) +## self.assertEqual(Bitxor, Bitxor_v) +## self.assertEqual(FloorDiv, FloorDiv_v) +## self.assertEqual(LeftShift, LeftShift_v) +## self.assertEqual(Modulo, Modulo_v) +## self.assertEqual(Mul, Mul_v) +## self.assertEqual(RightShift, RightShift_v) +## self.assertEqual(Sub, Sub_v) +## self.assertEqual(Sum, Sum_v) + +## return augmops, augmops_v, stimulus(), check() + + +## def testAugmOps(self): +## for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)): +## sim = self.augmBench(m, n) +## Simulation(sim).run() +