verilog test

myhdl/test/toVHDL/test_bin2gray.py

@@ -56,7 +56,7 @@ def bin2grayBench(width, bin2gray):
             #print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
             #print bin(G, width)
             #print bin(G_v, width)
-            print "%0d" % G
+            print "%d" % G
 
 
     return stimulus, bin2gray_inst

myhdl/test/toVHDL/test_custom.py

@@ -172,6 +172,7 @@ def inc3(count, enable, clock, reset, n):
 
 
 def clockGen(clock):
+    clock.next = 1
     while 1:
         yield delay(10)
         clock.next = not clock

myhdl/test/toVHDL/test_inc.py

@@ -121,7 +121,7 @@ def IncBench(inc):
 
     @instance
     def clockgen():
-        clock.next = 0
+        clock.next = 1
         for i in range(NR_CYCLES):
             yield delay(10)
             clock.next = not clock

myhdl/test/toVHDL/test_ram.py

@@ -136,6 +136,7 @@ def RamBench(ram, depth=128):
 
     @instance
     def clkgen():
+        clk.next = 1
         while True:
             yield delay(10)
             clk.next = not clk

myhdl/test/toVHDL/test_rom.py

@@ -75,6 +75,7 @@ def RomBench(rom):
 
     @instance
     def clkgen():
+        clk.next = 1
         while 1:
             yield delay(10)
             clk.next = not clk