From 1ae2c2e9f55643f356c015bd3bf3071c3735e322 Mon Sep 17 00:00:00 2001
From: jand <none@none>
Date: Thu, 28 Jun 2007 20:34:19 +0000
Subject: [PATCH] verilog test

---
 myhdl/test/toVHDL/test_bin2gray.py | 2 +-
 myhdl/test/toVHDL/test_custom.py   | 1 +
 myhdl/test/toVHDL/test_inc.py      | 2 +-
 myhdl/test/toVHDL/test_ram.py      | 1 +
 myhdl/test/toVHDL/test_rom.py      | 1 +
 5 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/myhdl/test/toVHDL/test_bin2gray.py b/myhdl/test/toVHDL/test_bin2gray.py
index 4cf66644..76ae0d65 100644
--- a/myhdl/test/toVHDL/test_bin2gray.py
+++ b/myhdl/test/toVHDL/test_bin2gray.py
@@ -56,7 +56,7 @@ def bin2grayBench(width, bin2gray):
             #print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
             #print bin(G, width)
             #print bin(G_v, width)
-            print "%0d" % G
+            print "%d" % G
 
 
     return stimulus, bin2gray_inst
diff --git a/myhdl/test/toVHDL/test_custom.py b/myhdl/test/toVHDL/test_custom.py
index f064812c..d58918f9 100644
--- a/myhdl/test/toVHDL/test_custom.py
+++ b/myhdl/test/toVHDL/test_custom.py
@@ -172,6 +172,7 @@ def inc3(count, enable, clock, reset, n):
 
 
 def clockGen(clock):
+    clock.next = 1
     while 1:
         yield delay(10)
         clock.next = not clock
diff --git a/myhdl/test/toVHDL/test_inc.py b/myhdl/test/toVHDL/test_inc.py
index 7c9cf363..7accf04e 100644
--- a/myhdl/test/toVHDL/test_inc.py
+++ b/myhdl/test/toVHDL/test_inc.py
@@ -121,7 +121,7 @@ def IncBench(inc):
 
     @instance
     def clockgen():
-        clock.next = 0
+        clock.next = 1
         for i in range(NR_CYCLES):
             yield delay(10)
             clock.next = not clock
diff --git a/myhdl/test/toVHDL/test_ram.py b/myhdl/test/toVHDL/test_ram.py
index d39794e6..73415120 100644
--- a/myhdl/test/toVHDL/test_ram.py
+++ b/myhdl/test/toVHDL/test_ram.py
@@ -136,6 +136,7 @@ def RamBench(ram, depth=128):
 
     @instance
     def clkgen():
+        clk.next = 1
         while True:
             yield delay(10)
             clk.next = not clk
diff --git a/myhdl/test/toVHDL/test_rom.py b/myhdl/test/toVHDL/test_rom.py
index ae582adf..da09349e 100644
--- a/myhdl/test/toVHDL/test_rom.py
+++ b/myhdl/test/toVHDL/test_rom.py
@@ -75,6 +75,7 @@ def RomBench(rom):
 
     @instance
     def clkgen():
+        clk.next = 1
         while 1:
             yield delay(10)
             clk.next = not clk