From 1b4e8706b2d0592da16716858b41fa309a45c134 Mon Sep 17 00:00:00 2001
From: Jan Decaluwe <jan@jandecaluwe.com>
Date: Fri, 2 Jul 2010 23:20:24 +0200
Subject: [PATCH] support for user-requested instances

---
 myhdl/_enum.py             |  1 +
 myhdl/_extractHierarchy.py | 48 ++++++++++++++++++++++++++++++--------
 2 files changed, 39 insertions(+), 10 deletions(-)

diff --git a/myhdl/_enum.py b/myhdl/_enum.py
index e0a48d46..30875bd8 100644
--- a/myhdl/_enum.py
+++ b/myhdl/_enum.py
@@ -102,6 +102,7 @@ def enum(*names, **kwargs):
             self.__dict__['_nritems'] = len(names)
             self.__dict__['_codedict'] = codedict
             self.__dict__['_encoding'] = encoding
+            self.__dict__['_name'] = None
             for index, name in enumerate(names):
                 val = codedict[name]
                 self.__dict__[name] = EnumItem(index, name, val, self)
diff --git a/myhdl/_extractHierarchy.py b/myhdl/_extractHierarchy.py
index 55a77fca..93c58310 100644
--- a/myhdl/_extractHierarchy.py
+++ b/myhdl/_extractHierarchy.py
@@ -85,11 +85,12 @@ _userCodeMap = {'verilog' : {},
                }
 
 class _UserCode(object):
-    __slots__ = ['code', 'namespace', 'sourcefile', 'funcname', 'sourceline']
-    def __init__(self, code, namespace, sourcefile, funcname, sourceline):
+    __slots__ = ['code', 'namespace', 'funcname', 'func', 'sourcefile', 'sourceline']
+    def __init__(self, code, namespace, funcname, func, sourcefile, sourceline):
         self.code = code
         self.namespace = namespace
         self.sourcefile = sourcefile
+        self.func = func
         self.funcname = funcname
         self.sourceline = sourceline
 
@@ -113,18 +114,45 @@ class _UserVhdlCode(_UserCode):
     def raiseError(self, msg, info):
         raise ToVHDLError("Error in user defined VHDL code", msg, info)
     
-    
-_UserVerilogInstance = _UserVerilogCode
-_UserVhdlInstance = _UserVhdlCode
+class _UserVerilogInstance(_UserVerilogCode):
+    def __str__(self):
+        args = inspect.getargspec(self.func)[0]
+        s = "%s %s(" % (self.funcname, self.code)
+        sep = ''
+        for arg in args:
+            if arg in self.namespace and isinstance(self.namespace[arg], _Signal):
+                signame = self.namespace[arg]._name
+                s += sep
+                sep = ','
+                s += "\n    .%s(%s)" % (arg, signame)
+        s += "\n)\n"
+        return s
 
-def _addUserCode(specs, arg, funcname, frame):
+class _UserVhdlInstance(_UserVhdlCode):
+    def __str__(self):
+        args = inspect.getargspec(self.func)[0]
+        s = "%s: entity work.%s(MyHDL)\n" % (self.code, self.funcname)
+        s += "    port map ("
+        sep = ''
+        for arg in args:
+            if arg in self.namespace and isinstance(self.namespace[arg], _Signal):
+                signame = self.namespace[arg]._name
+                s += sep
+                sep = ','
+                s += "\n        %s=>%s" % (arg, signame)
+        s += "\n    );\n"
+        return s
+   
+    
+
+def _addUserCode(specs, arg, funcname, func, frame):
     classMap = {
                 '__verilog__' : _UserVerilogCode,
                 '__vhdl__' :_UserVhdlCode,
                 'verilog_code' : _UserVerilogCode,
                 'vhdl_code' :_UserVhdlCode,
-                'verilog_code' : _UserVerilogInstance,
-                'vhdl_code' :_UserVhdlInstance,
+                'verilog_instance' : _UserVerilogInstance,
+                'vhdl_instance' :_UserVhdlInstance,
                
                }
     namespace = frame.f_globals.copy()
@@ -146,7 +174,7 @@ def _addUserCode(specs, arg, funcname, frame):
         if spec:
             assert id(arg) not in _userCodeMap[hdl]
             code = specs[spec]
-            _userCodeMap[hdl][id(arg)] = classMap[spec](code, namespace, sourcefile, funcname, sourceline)
+            _userCodeMap[hdl][id(arg)] = classMap[spec](code, namespace, funcname, func, sourcefile, sourceline)
          
 
 class _CallFuncVisitor(object):
@@ -246,7 +274,7 @@ class _HierExtr(object):
                         if func and hasattr(func, spec) and getattr(func, spec):
                             specs[spec] = getattr(func, spec)
                     if specs: 
-                        _addUserCode(specs, arg, funcname, frame)
+                        _addUserCode(specs, arg, funcname, func, frame)
                 # building hierarchy only makes sense if there are generators
                 if isGenSeq and arg:
                     sigdict = {}