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https://github.com/myhdl/myhdl.git
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astNode
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jand
parent
24c8fbe188
commit
1bc6321c96
@ -28,7 +28,7 @@ __date__ = "$Date$"
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import inspect
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import operator
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import compiler
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from compiler import ast
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from compiler import ast as astNode
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from sets import Set
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from types import GeneratorType, FunctionType, ClassType
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from cStringIO import StringIO
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@ -166,13 +166,12 @@ def _analyzeGens(top, genNames):
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ast = compiler.parse(s)
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ast.sourcefile = inspect.getsourcefile(f)
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ast.lineoffset = inspect.getsourcelines(f)[1]-1
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symdict = f.f_globals.copy()
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symdict.update(f.f_locals)
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ast.symdict = symdict
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ast.symdict = f.f_globals.copy()
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ast.symdict.update(f.f_locals)
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ast.name = genNames.get(id(g), genLabel.next() + "_BLOCK")
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v = _NotSupportedVisitor(ast)
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compiler.walk(ast, v)
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v = _AnalyzeBlockVisitor(ast.symdict, ast.sourcefile, ast.lineoffset)
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v = _AnalyzeBlockVisitor(ast)
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compiler.walk(ast, v)
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ast.sigdict = v.sigdict
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ast.vardict = v.vardict
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@ -204,7 +203,7 @@ class _ToVerilogMixin(object):
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raise ToVerilogError(kind, msg, info)
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def require(self, node, test, msg=""):
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assert isinstance(node, ast.Node)
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assert isinstance(node, astNode.Node)
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if not test:
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self.raiseError(node, _error.Requirement, msg)
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@ -324,10 +323,10 @@ class ReferenceStack(list):
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class _AnalyzeVisitor(_ToVerilogMixin):
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def __init__(self, symdict, sourcefile, lineoffset):
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self.sourcefile = sourcefile
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self.lineoffset = lineoffset
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self.symdict = symdict
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def __init__(self, ast):
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self.sourcefile = ast.sourcefile
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self.lineoffset = ast.lineoffset
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self.symdict = ast.symdict
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self.vardict = {}
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self.inputs = Set()
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self.outputs = Set()
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@ -408,7 +407,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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def visitAssign(self, node, access=OUTPUT, *args):
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target, expr = node.nodes[0], node.expr
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self.visit(target, OUTPUT)
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if isinstance(target, ast.AssName):
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if isinstance(target, astNode.AssName):
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self.visit(expr, INPUT, DECLARATION)
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node.kind = DECLARATION
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n = target.name
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@ -467,14 +466,14 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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s = inspect.getsource(func)
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s = s.lstrip()
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ast = compiler.parse(s)
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print ast
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# print ast
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ast.name = genLabel.next() + "_" + func.__name__
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ast.sourcefile = inspect.getsourcefile(func)
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ast.lineoffset = inspect.getsourcelines(func)[1]-1
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ast.symdict = func.func_globals.copy()
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v = _NotSupportedVisitor(ast)
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compiler.walk(ast, v)
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v = _AnalyzeFuncVisitor(ast.symdict, ast.sourcefile, ast.lineoffset, node.args)
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v = _AnalyzeFuncVisitor(ast, node.args)
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compiler.walk(ast, v)
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ast.sigdict = v.sigdict
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ast.vardict = v.vardict
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@ -485,13 +484,11 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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ast.kind = v.kind
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node.ast = ast
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for i, arg in enumerate(node.args):
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if isinstance(arg, compiler.ast.Keyword):
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if isinstance(arg, astNode.Keyword):
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n = arg.name
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else: # Name
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n = ast.argnames[i]
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if n in ast.outputs:
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print "ARG"
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print arg
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self.visit(arg, OUTPUT)
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if n in ast.inputs:
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self.visit(arg, INPUT)
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@ -534,7 +531,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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def visitGetattr(self, node, *args):
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self.visit(node.expr, *args)
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assert isinstance(node.expr, ast.Name)
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assert isinstance(node.expr, astNode.Name)
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assert node.expr.name in self.symdict
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obj = self.symdict[node.expr.name]
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if str(type(obj)) == "<class 'myhdl._enum.Enum'>":
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@ -614,9 +611,9 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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self.refStack.push()
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self.visit(node.body, *args)
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self.refStack.pop()
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if isinstance(node.test, ast.Const) and \
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if isinstance(node.test, astNode.Const) and \
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node.test.value == True and \
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isinstance(node.body.nodes[0], ast.Yield):
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isinstance(node.body.nodes[0], astNode.Yield):
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node.kind = ALWAYS
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self.require(node, node.else_ is None, "while-else not supported")
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self.labelStack.pop()
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@ -625,16 +622,16 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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class _AnalyzeBlockVisitor(_AnalyzeVisitor):
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def __init__(self, symdict, sourcefile, lineoffset):
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_AnalyzeVisitor.__init__(self, symdict, sourcefile, lineoffset)
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def __init__(self, ast):
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_AnalyzeVisitor.__init__(self, ast)
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self.sigdict = sigdict = {}
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for n, v in symdict.items():
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for n, v in self.symdict.items():
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if isinstance(v, Signal):
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sigdict[n] = v
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def visitFunction(self, node, *args):
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self.refStack.push()
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print node.code
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# print node.code
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self.visit(node.code)
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self.kind = ALWAYS
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for n in node.code.nodes[:-1]:
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@ -665,8 +662,8 @@ class _AnalyzeBlockVisitor(_AnalyzeVisitor):
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class _AnalyzeFuncVisitor(_AnalyzeVisitor):
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def __init__(self, symdict, sourcefile, lineoffset, args):
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_AnalyzeVisitor.__init__(self, symdict, sourcefile, lineoffset)
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def __init__(self, ast, args):
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_AnalyzeVisitor.__init__(self, ast)
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self.sigdict = sigdict = {}
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self.args = args
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self.argnames = []
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@ -678,7 +675,7 @@ class _AnalyzeFuncVisitor(_AnalyzeVisitor):
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self.refStack.push()
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argnames = node.argnames
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for i, arg in enumerate(self.args):
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if isinstance(arg, ast.Keyword):
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if isinstance(arg, astNode.Keyword):
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n = arg.name
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self.symdict[n] = getObj(arg.expr)
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else: # Name
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@ -693,9 +690,9 @@ class _AnalyzeFuncVisitor(_AnalyzeVisitor):
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def visitReturn(self, node, *args):
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self.visit(node.value, INPUT, DECLARATION, *args)
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if isinstance(node.value, ast.Const) and node.value.value is None:
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if isinstance(node.value, astNode.Const) and node.value.value is None:
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obj = None
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elif isinstance(node.value, ast.Name) and node.value.name is None:
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elif isinstance(node.value, astNode.Name) and node.value.name is None:
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obj = None
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elif node.value.obj is not None:
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obj = node.value.obj
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@ -998,7 +995,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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def visitCallFunc(self, node):
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fn = node.node
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assert isinstance(fn, ast.Name)
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assert isinstance(fn, astNode.Name)
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f = getObj(fn)
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opening, closing = '(', ')'
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if f is bool:
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@ -1054,7 +1051,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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expr = node.expr
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self.visit(expr)
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# ugly hack to detect an orphan "task" call
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if isinstance(expr, ast.CallFunc) and hasattr(expr, 'ast'):
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if isinstance(expr, astNode.CallFunc) and hasattr(expr, 'ast'):
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self.write(';')
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def visitFor(self, node):
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@ -1062,7 +1059,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.labelStack.append(node.loopLabel)
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var = node.assign.name
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cf = node.list
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self.require(node, isinstance(cf, ast.CallFunc), "Expected (down)range call")
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self.require(node, isinstance(cf, astNode.CallFunc), "Expected (down)range call")
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f = getObj(cf.node)
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self.require(node, f in (range, downrange), "Expected (down)range call")
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args = cf.args
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@ -1123,7 +1120,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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raise AssertionError("To be implemented in subclass")
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def visitGetattr(self, node):
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assert isinstance(node.expr, ast.Name)
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assert isinstance(node.expr, astNode.Name)
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assert node.expr.name in self.symdict
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obj = self.symdict[node.expr.name]
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if type(obj) is Signal:
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@ -1208,7 +1205,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.write("disable %s;" % self.returnLabel)
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def visitSlice(self, node):
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if isinstance(node.expr, ast.CallFunc) and \
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if isinstance(node.expr, astNode.CallFunc) and \
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node.expr.node.obj is intbv:
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c = self.getVal(node)
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self.write("%s'h" % c._nrbits)
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@ -1232,7 +1229,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.writeline()
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self.visit(stmt)
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# ugly hack to detect an orphan "task" call
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if isinstance(stmt, ast.CallFunc) and hasattr(stmt, 'ast'):
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if isinstance(stmt, astNode.CallFunc) and hasattr(stmt, 'ast'):
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self.write(';')
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def visitSubscript(self, node):
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@ -1288,7 +1285,7 @@ class _ConvertAlwaysVisitor(_ConvertVisitor):
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def visitFunction(self, node):
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w = node.code.nodes[-1]
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assert isinstance(w.body.nodes[0], ast.Yield)
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assert isinstance(w.body.nodes[0], astNode.Yield)
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sl = w.body.nodes[0].value
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self.inYield = True
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self.write("always @(")
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@ -1297,7 +1294,7 @@ class _ConvertAlwaysVisitor(_ConvertVisitor):
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self.write(") begin: %s" % self.name)
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self.indent()
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self.writeDeclarations()
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assert isinstance(w.body, ast.Stmt)
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assert isinstance(w.body, astNode.Stmt)
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for stmt in w.body.nodes[1:]:
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self.writeline()
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self.visit(stmt)
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@ -1340,9 +1337,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
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elif hasattr(obj, '_nrbits'):
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self.write("[%s-1:0]" % obj._nrbits)
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else:
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print "HERE"
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print type(obj)
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raise AssertionError("unexpected type")
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raise AssertionError("unexpected type")
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def writeInputDeclarations(self):
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for name in self.argnames:
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