mirror of
https://github.com/myhdl/myhdl.git
synced 2024-12-14 07:44:38 +08:00
fine-grained signed arithmetic
This commit is contained in:
jand
parent
26a43394c4
commit
1c3a13c946
10
MANIFEST.in
10
MANIFEST.in
@ -8,10 +8,10 @@ global-include makefile*
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global-include *.v
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prune dist
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prune doc
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graft doc/html/manual
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graft doc/html/icons
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graft doc/html/whatsnew*
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include doc/paper-a4/*.pdf
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include doc/paper-letter/*.pdf
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#graft doc/html/manual
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#graft doc/html/icons
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#graft doc/html/whatsnew*
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#include doc/paper-a4/*.pdf
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#include doc/paper-letter/*.pdf
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prune myhdl/experiments
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exclude myhdl/test/toVerilog/*.v
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@ -71,7 +71,7 @@ _error.ListElementNotUnique = "List contains Signals that are not unique to it"
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_access = enum("INPUT", "OUTPUT", "INOUT", "UNKNOWN")
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_kind = enum("NORMAL", "DECLARATION", "ALWAYS", "INITIAL", "ALWAYS_COMB", "SIMPLE_ALWAYS_COMB", "ALWAYS_DECO", "TASK", "REG")
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_context = enum("BOOLEAN", "YIELD", "PRINT" ,"EXPR", "UNKNOWN")
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_context = enum("BOOLEAN", "YIELD", "PRINT" ,"SIGNED", "UNKNOWN")
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class _ToVerilogMixin(object):
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@ -48,9 +48,6 @@ from myhdl._extractHierarchy import _isMem, _CustomVerilog
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myhdlObjects = myhdl.__dict__.values()
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builtinObjects = __builtin__.__dict__.values()
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_signed = False
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def _isSigned():
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return _signed
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def _makeName(n, prefixes):
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if len(prefixes) > 1:
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@ -64,7 +61,6 @@ def _makeName(n, prefixes):
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return name
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def _analyzeSigs(hierarchy):
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global _signed
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curlevel = 0
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siglist = []
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memlist = []
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@ -74,24 +70,15 @@ def _analyzeSigs(hierarchy):
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delta = curlevel - level
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curlevel = level
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assert(delta >= -1)
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#print
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#print curlevel
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#print delta
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#print prefixes
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if delta == -1:
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prefixes.append(name)
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else:
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prefixes = prefixes[:curlevel-1]
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prefixes.append(name)
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assert prefixes[-1] == name
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#print prefixes
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# signals
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#print sigdict
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for n, s in sigdict.items():
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if s._name is not None:
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continue
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if s._min is not None and s._min < 0:
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_signed = True
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s._name = _makeName(n, prefixes)
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if not s._nrbits:
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raise ToVerilogError(_error.UndefinedBitWidth, s._name)
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@ -120,8 +107,6 @@ def _analyzeSigs(hierarchy):
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raise ToVerilogError(_error.InconsistentType, s._name)
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if s._nrbits != m.elObj._nrbits:
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raise ToVerilogError(_error.InconsistentBitWidth, s._name)
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if s._min is not None and s._min < 0:
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_signed = True
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return siglist, memlist
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@ -328,6 +313,11 @@ class _Rom(object):
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def __init__(self, rom):
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self.rom = rom
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def _isNegative(obj):
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if hasattr(obj, '_min') and (obj._min is not None) and (obj._min < 0):
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return True
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return False
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class _AnalyzeVisitor(_ToVerilogMixin):
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@ -350,18 +340,22 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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self.visit(node.left)
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self.visit(node.right)
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node.obj = int()
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node.signed = node.left.signed or node.right.signed
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visitAdd = binaryOp
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visitFloorDiv = binaryOp
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visitLeftShift = binaryOp
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visitMul = binaryOp
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visitPow = binaryOp
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visitPower = binaryOp
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visitMod = binaryOp
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visitRightShift = binaryOp
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visitSub = binaryOp
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def multiBitOp(self, node, *args):
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node.signed = False
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for n in node.nodes:
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self.visit(n)
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if n.signed:
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node.signed = True
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node.obj = None
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for n in node.nodes:
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if node.obj is None:
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@ -387,15 +381,19 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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def visitInvert(self, node, *args):
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self.visit(node.expr)
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node.obj = node.expr.obj
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node.signed = node.expr.signed
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def visitNot(self, node, *args):
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self.visit(node.expr)
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node.obj = bool()
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node.signed = node.expr.signed
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def visitUnaryAdd(self, node, *args):
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self.visit(node.expr)
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node.obj = int()
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node.signed = node.expr.signed
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def visitUnarySub(self, node, *args):
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self.visit(node.expr)
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node.obj = int()
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node.signed = node.expr.signed
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def visitAssAttr(self, node, access=_access.OUTPUT, *args):
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if node.attrname != 'next':
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@ -404,7 +402,6 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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self.visit(node.expr, _access.OUTPUT)
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def visitAssign(self, node, access=_access.OUTPUT, *args):
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global _signed
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target, expr = node.nodes[0], node.expr
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self.visit(target, _access.OUTPUT)
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if isinstance(target, astNode.AssName):
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@ -457,6 +454,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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argsAreInputs = True
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f = self.getObj(node.node)
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node.obj = None
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node.signed = False
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if type(f) is type and issubclass(f, intbv):
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node.obj = self.getVal(node)
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elif f is len:
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@ -517,7 +515,11 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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def visitCompare(self, node, *args):
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node.obj = bool()
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self.visitChildNodes(node)
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node.signed = False
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for n in node.getChildNodes():
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self.visit(n, *args)
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if n.signed:
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node.signed = True
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op, arg = node.ops[0]
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if op == '==':
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if isinstance(node.expr, astNode.Name) and \
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@ -525,6 +527,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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node.case = (node.expr.name, arg.obj)
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def visitConst(self, node, *args):
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node.signed = False
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if isinstance(node.value, int):
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node.obj = node.value
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else:
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@ -557,6 +560,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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assert isinstance(node.expr, astNode.Name)
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assert node.expr.name in self.ast.symdict
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node.obj = None
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node.signed = False
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obj = self.ast.symdict[node.expr.name]
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if isinstance(obj, Signal):
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if node.attrname in ('posedge', 'negedge'):
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@ -645,11 +649,13 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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node.obj = __builtin__.__dict__[n]
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else:
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pass
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node.signed = _isNegative(node.obj)
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def visitReturn(self, node, *args):
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self.raiseError(node, _error.NotSupported, "return statement")
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def visitSlice(self, node, access=_access.INPUT, kind=_kind.NORMAL, *args):
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node.signed = False
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self.visit(node.expr, access)
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node.obj = self.getObj(node.expr)
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if node.lower:
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@ -668,6 +674,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
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def visitSubscript(self, node, access=_access.INPUT, *args):
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node.signed = False
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self.visit(node.expr, access)
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assert len(node.subs) == 1
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self.visit(node.subs[0], _access.INPUT)
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@ -46,7 +46,7 @@ from myhdl._always import _Always
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from myhdl._toVerilog import _error, _access, _kind,_context, \
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_ToVerilogMixin, _Label
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from myhdl._toVerilog._analyze import _analyzeSigs, _analyzeGens, _analyzeTopFunc, \
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_Ram, _Rom, _isSigned
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_Ram, _Rom
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_converting = 0
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_profileFunc = None
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@ -234,16 +234,12 @@ def _getRangeString(s):
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return ''
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elif s._nrbits is not None:
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nrbits = s._nrbits
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if _isSigned():
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# add a sign bit to positive numbers
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if s._type is intbv and s._min >=0:
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nrbits += 1
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return "[%s:0] " % (nrbits-1)
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else:
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raise AssertionError
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def _getSignString(s):
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if _isSigned() and s._type is intbv:
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if s._min is not None and s._min < 0:
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return "signed "
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else:
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return ''
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@ -301,8 +297,9 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.write("reg [%s-1:0] %s [0:%s-1]" % (obj.elObj._nrbits, name, obj.depth))
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elif hasattr(obj, '_nrbits'):
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s = ""
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if isinstance(obj, intbv) and obj._min < 0:
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s = "signed "
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if isinstance(obj, (intbv, Signal)):
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if obj._min is not None and obj._min < 0:
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s = "signed "
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self.write("%s%s[%s-1:0] %s" % (dir, s, obj._nrbits, name))
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else:
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raise AssertionError("var %s has unexpected type %s" % (name, type(obj)))
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@ -331,10 +328,13 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.ind = self.ind[:-4]
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def binaryOp(self, node, op=None):
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context = None
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if node.signed:
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context = _context.SIGNED
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self.write("(")
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self.visit(node.left, _context.EXPR)
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self.visit(node.left, context)
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self.write(" %s " % op)
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self.visit(node.right, _context.EXPR)
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self.visit(node.right, context)
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self.write(")")
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def visitAdd(self, node, *args):
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self.binaryOp(node, '+')
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@ -374,7 +374,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.visit(node.nodes[0])
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for n in node.nodes[1:]:
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self.write(" %s " % op)
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self.visit(n, _context.EXPR)
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self.visit(n)
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self.write(")")
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def visitAnd(self, node, *args):
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self.multiOp(node, '&&')
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@ -387,19 +387,19 @@ class _ConvertVisitor(_ToVerilogMixin):
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def visitOr(self, node, *args):
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self.multiOp(node, '||')
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def unaryOp(self, node, op):
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def unaryOp(self, node, op, context):
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self.checkOpWithNegIntbv(node.expr, op)
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self.write("(%s" % op)
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self.visit(node.expr, _context.EXPR)
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self.visit(node.expr, context)
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self.write(")")
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def visitInvert(self, node, *args):
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self.unaryOp(node, '~')
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def visitNot(self, node, *args):
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self.unaryOp(node, '!')
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def visitUnaryAdd(self, node, *args):
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self.unaryOp(node, '+')
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def visitUnarySub(self, node, *args):
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self.unaryOp(node, '-')
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def visitInvert(self, node, context=None, *args):
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self.unaryOp(node, '~', context)
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def visitNot(self, node, context=None, *args):
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self.unaryOp(node, '!', context)
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def visitUnaryAdd(self, node, context=None, *args):
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self.unaryOp(node, '+', context)
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def visitUnarySub(self, node, context=None, *args):
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self.unaryOp(node, '-', context)
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def visitAssAttr(self, node, *args):
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assert node.attrname == 'next'
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@ -496,6 +496,9 @@ class _ConvertVisitor(_ToVerilogMixin):
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return
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elif f in (int, long):
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opening, closing = '', ''
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elif f is intbv:
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self.visit(node.args[0])
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return
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elif type(f) is ClassType and issubclass(f, Exception):
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self.write(f.__name__)
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elif f in (posedge, negedge):
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@ -523,11 +526,14 @@ class _ConvertVisitor(_ToVerilogMixin):
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compiler.walk(node.ast, v)
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def visitCompare(self, node, *args):
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context = None
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if node.signed:
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context = _context.SIGNED
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self.write("(")
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self.visit(node.expr)
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self.visit(node.expr, context)
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op, code = node.ops[0]
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self.write(" %s " % op)
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self.visit(code)
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self.visit(code, context)
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self.write(")")
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def visitConst(self, node, context=None, *args):
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@ -697,54 +703,50 @@ class _ConvertVisitor(_ToVerilogMixin):
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def visitModule(self, node, *args):
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for stmt in node.node.nodes:
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self.visit(stmt)
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def writeName(self, name, context, isBool):
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addSignBit = isBool and _isSigned() and context == _context.EXPR
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if addSignBit:
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self.write("$signed({1'b0, ")
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self.write(name)
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if addSignBit:
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self.write("})")
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def visitName(self, node, context=None, *args):
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addSignBit = False
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isMixedExpr = (not node.signed) and (context == _context.SIGNED)
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n = node.name
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if n == 'False':
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self.write("0")
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s = "0"
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elif n == 'True':
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self.write("1")
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s = "1"
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elif n in self.ast.vardict:
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obj = self.ast.vardict[n]
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isBool = isinstance(obj, bool)
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self.writeName(n, context, isBool)
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addSignBit = isMixedExpr
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s = n
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elif n in self.ast.argnames:
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assert n in self.ast.symdict
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obj = self.ast.symdict[n]
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isBool = isinstance(obj, bool) or (isinstance(obj, Signal) and obj._type is bool)
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self.writeName(n, context, isBool)
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addSignBit = isMixedExpr
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s = n
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elif n in self.ast.symdict:
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obj = self.ast.symdict[n]
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if isinstance(obj, bool):
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self.write("%s" % int(obj))
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s = "%s" % int(obj)
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elif isinstance(obj, int):
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self.write(str(obj))
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s = str(obj)
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elif isinstance(obj, Signal):
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isBool = obj._type is bool
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assert obj._name
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self.writeName(obj._name, context, isBool)
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addSignBit = isMixedExpr
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s = str(obj)
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elif _isMem(obj):
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m = _getMemInfo(obj)
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assert m.name
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if not m.decl:
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self.raiseError(node, _error.ListElementNotUnique, m.name)
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self.write(m.name)
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s = m.name
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elif str(type(obj)) == "<class 'myhdl._enum.EnumItem'>":
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self.write(obj._toVerilog())
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s = obj._toVerilog()
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elif type(obj) is ClassType and issubclass(obj, Exception):
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self.write(n)
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s = n
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else:
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self.raiseError(node, _error.UnsupportedType, "%s, %s" % (n, type(obj)))
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else:
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raise AssertionError("name ref: %s" % n)
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if addSignBit:
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self.write("$signed({1'b0, ")
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self.write(s)
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if addSignBit:
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self.write("})")
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def visitPass(self, node, *args):
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self.write("// pass")
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@ -774,14 +776,15 @@ class _ConvertVisitor(_ToVerilogMixin):
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def visitReturn(self, node, *args):
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self.write("disable %s;" % self.returnLabel)
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def visitSlice(self, node, *args):
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def visitSlice(self, node, context=None, *args):
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if isinstance(node.expr, astNode.CallFunc) and \
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node.expr.node.obj is intbv:
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c = self.getVal(node)
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self.write("%s'h" % c._nrbits)
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self.write("%x" % c._val)
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return
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if node.flags == 'OP_APPLY' and _isSigned():
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addSignBit = (node.flags == 'OP_APPLY') and (context == _context.SIGNED)
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if addSignBit:
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self.write("$signed({1'b0, ")
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self.visit(node.expr)
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# special shortcut case for [:] slice
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@ -798,7 +801,7 @@ class _ConvertVisitor(_ToVerilogMixin):
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else:
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self.visit(node.upper)
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self.write("]")
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if node.flags == 'OP_APPLY' and _isSigned():
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if addSignBit:
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self.write("})")
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def visitStmt(self, node, *args):
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@ -809,15 +812,16 @@ class _ConvertVisitor(_ToVerilogMixin):
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if isinstance(stmt, astNode.CallFunc) and hasattr(stmt, 'ast'):
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self.write(';')
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def visitSubscript(self, node, *args):
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if node.flags == 'OP_APPLY' and _isSigned():
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def visitSubscript(self, node, context=None, *args):
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addSignBit = (node.flags == 'OP_APPLY') and (context == _context.SIGNED)
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if addSignBit:
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self.write("$signed({1'b0, ")
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self.visit(node.expr)
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self.write("[")
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assert len(node.subs) == 1
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self.visit(node.subs[0])
|
||||
self.write("]")
|
||||
if node.flags == 'OP_APPLY' and _isSigned():
|
||||
if addSignBit:
|
||||
self.write("})")
|
||||
|
||||
def visitTuple(self, node, context=None, *args):
|
||||
|
||||
@ -54,6 +54,28 @@ def dec(count, enable, clock, reset, n):
|
||||
count.next = count - 1
|
||||
return decProcess()
|
||||
|
||||
|
||||
def decFunc(count, enable, clock, reset, n):
|
||||
|
||||
def decFuncFunc(cnt):
|
||||
count_next = intbv(0, min=-n, max=n)
|
||||
if count == -n:
|
||||
count_next[:] = n-1
|
||||
else:
|
||||
count_next[:] = cnt - 1
|
||||
return count_next
|
||||
|
||||
@always(clock.posedge, reset.negedge)
|
||||
def decFuncGen():
|
||||
if reset == ACTIVE_LOW:
|
||||
count.next = 0
|
||||
else:
|
||||
if enable:
|
||||
count.next = decFuncFunc(count)
|
||||
|
||||
return decFuncGen
|
||||
|
||||
|
||||
def decTask(count, enable, clock, reset, n):
|
||||
|
||||
def decTaskFunc(cnt, enable, reset, n):
|
||||
@ -163,14 +185,16 @@ class TestDec(TestCase):
|
||||
return sim
|
||||
|
||||
def testDecRef(self):
|
||||
""" Check decrement operation """
|
||||
sim = self.bench(decRef)
|
||||
sim.run(quiet=1)
|
||||
|
||||
def testDec(self):
|
||||
""" Check decrement operation """
|
||||
sim = self.bench(dec)
|
||||
sim.run(quiet=1)
|
||||
|
||||
def testDecFunc(self):
|
||||
sim = self.bench(decFunc)
|
||||
sim.run(quiet=1)
|
||||
|
||||
## signed inout in task doesn't work yet in Icarus
|
||||
## def testDecTask(self):
|
||||
|
||||
@ -47,6 +47,21 @@ def inc(count, enable, clock, reset, n):
|
||||
count.next = (count + 1) % n
|
||||
return incProcess
|
||||
|
||||
def inc2(count, enable, clock, reset, n):
|
||||
|
||||
@always(clock.posedge, reset.negedge)
|
||||
def incProcess():
|
||||
if reset == ACTIVE_LOW:
|
||||
count.next = 0
|
||||
else:
|
||||
if enable:
|
||||
if count == n:
|
||||
count.next = 0
|
||||
else:
|
||||
count.next = count + 1
|
||||
return incProcess
|
||||
|
||||
|
||||
def incTask(count, enable, clock, reset, n):
|
||||
|
||||
def incTaskFunc(cnt, enable, reset, n):
|
||||
@ -155,6 +170,11 @@ class TestInc(TestCase):
|
||||
sim = self.bench(inc)
|
||||
sim.run(quiet=1)
|
||||
|
||||
def testInc2(self):
|
||||
""" Check increment operation """
|
||||
sim = self.bench(inc2)
|
||||
sim.run(quiet=1)
|
||||
|
||||
def testIncTask(self):
|
||||
sim = self.bench(incTask)
|
||||
sim.run(quiet=1)
|
||||
|
||||
@ -482,6 +482,84 @@ class TestAugmOps(TestCase):
|
||||
Simulation(sim).run()
|
||||
|
||||
|
||||
def expressions(a, b, clk):
|
||||
|
||||
c = Signal(intbv(0, min=0, max=47))
|
||||
e = Signal(bool())
|
||||
|
||||
@instance
|
||||
def logic():
|
||||
|
||||
d = intbv(0, min=-23, max=43)
|
||||
d[:] = -17
|
||||
|
||||
c.next = 5
|
||||
yield clk.posedge
|
||||
a.next = c + 1
|
||||
b.next = c + 1
|
||||
yield clk.posedge
|
||||
a.next = c + -10
|
||||
b.next = c + -1
|
||||
yield clk.posedge
|
||||
a.next = c < -10
|
||||
b.next = c < -1
|
||||
yield clk.posedge
|
||||
a.next = d + c
|
||||
b.next = d >= c
|
||||
yield clk.posedge
|
||||
# a.next = d & c
|
||||
# b.next = c + (d & c)
|
||||
yield clk.posedge
|
||||
a.next = d + -c
|
||||
b.next = c + (-d)
|
||||
yield clk.posedge
|
||||
a.next = -d
|
||||
yield clk.posedge
|
||||
a.next = -c
|
||||
yield clk.posedge
|
||||
|
||||
|
||||
yield clk.posedge
|
||||
raise StopSimulation
|
||||
|
||||
return logic
|
||||
|
||||
def expressions_v(a, b, clk):
|
||||
return setupCosimulation(**locals())
|
||||
|
||||
|
||||
class TestExpressions(TestCase):
|
||||
|
||||
def bench(self):
|
||||
|
||||
a, a_v = [Signal(intbv(0, min=-34, max=47)) for i in range(2)]
|
||||
b, b_v = [Signal(intbv(0, min=0, max=47)) for i in range(2)]
|
||||
clk = Signal(bool())
|
||||
|
||||
expr = toVerilog(expressions, a, b, clk)
|
||||
expr_v = toVerilog(expressions, a_v, b_v, clk)
|
||||
|
||||
@instance
|
||||
def check():
|
||||
while 1:
|
||||
yield clk.posedge
|
||||
yield delay(1)
|
||||
self.assertEqual(a, a_v)
|
||||
# print a
|
||||
# print a_v
|
||||
self.assertEqual(b, b_v)
|
||||
|
||||
@always(delay(10))
|
||||
def clkgen():
|
||||
clk.next = not clk
|
||||
|
||||
return expr, expr_v, check, clkgen
|
||||
|
||||
def testExpressions(self):
|
||||
sim = self.bench()
|
||||
Simulation(sim).run()
|
||||
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
unittest.main()
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user