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implmented SliceSignal conversion through slice/index names directly

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This commit is contained in:
Jan Decaluwe 2009-06-19 12:37:09 +02:00
parent 5ec4df7ca9
commit 1e34cf5f36
6 changed files with 51 additions and 23 deletions
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40
myhdl/_ShadowSignal.py
View File

@ -39,7 +39,7 @@ class _ShadowSignal(_Signal):
def __init__(self, val):
_Signal.__init__(self, val)
self.driven = True
self._driven = True
# remove next attribute assignment
next = property(_Signal._get_next, None, None, "'next' access methods")
@ -60,36 +60,48 @@ class _SliceSignal(_ShadowSignal):
self._left = left
self._right = right
if right is None:
gen = self.genfuncIndex()
gen = self._genfuncIndex()
else:
gen = self.genfuncSlice()
gen = self._genfuncSlice()
self._waiter = _SignalWaiter(gen)
def genfuncIndex(self):
def _genfuncIndex(self):
sig, index = self._sig, self._left
set_next = _ShadowSignal._set_next
while 1:
set_next(self, sig[index])
yield sig
def genfuncSlice(self):
def _genfuncSlice(self):
sig, left, right = self._sig, self._left, self._right
set_next = _Signal._set_next
while 1:
set_next(self, sig[left:right])
yield sig
def toVerilog(self):
if self._right is None:
return "assign %s = %s[%s];" % (self._name, self._sig._name, self._left)
def _setName(self, hdl):
if self._right is None:
if hdl == 'Verilog':
self._name = "%s[%s]" % (self._sig._name, self._left)
else:
self._name = "%s(%s)" % (self._sig._name, self._left)
else:
return "assign %s = %s[%s-1:%s];" % (self._name, self._sig._name, self._left, self._right)
if hdl == 'Verilog':
self._name = "%s[%s-1:%s]" % (self._sig._name, self._left, self._right)
else:
self._name = "%s(%s-1 downto %s)" % (self._sig._name, self._left, self._right)
def toVHDL(self):
if self._right is None:
return "%s <= %s(%s);" % (self._name, self._sig._name, self._left)
else:
return "%s <= %s(%s-1 downto %s);" % (self._name, self._sig._name, self._left, self._right)
# def toVerilog(self):
# if self._right is None:
# return "assign %s = %s[%s];" % (self._name, self._sig._name, self._left)
# else:
# return "assign %s = %s[%s-1:%s];" % (self._name, self._sig._name, self._left, self._right)
# def toVHDL(self):
# if self._right is None:
# return "%s <= %s(%s);" % (self._name, self._sig._name, self._left)
# else:
# return "%s <= %s(%s-1 downto %s);" % (self._name, self._sig._name, self._left, self._right)

10
myhdl/_Signal.py
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@ -105,7 +105,7 @@ class _Signal(object):
'_eventWaiters', '_posedgeWaiters', '_negedgeWaiters',
'_code', '_tracing', '_nrbits', '_checkVal', '_setNextVal',
'_printVcd', '_driven' ,'_read', '_name', '_used', '_inList',
'_waiter', 'toVHDL', 'toVerilog'
'_waiter', 'toVHDL', 'toVerilog', '_slicesigs'
)
@ -152,6 +152,7 @@ class _Signal(object):
self._posedgeWaiters = _PosedgeWaiterList(self)
self._negedgeWaiters = _NegedgeWaiterList(self)
self._code = ""
self._slicesigs = []
self._tracing = 0
_signals.append(self)
@ -161,6 +162,8 @@ class _Signal(object):
del self._negedgeWaiters[:]
self._next = self._val = self._init
self._name = self._read = self._driven = None
for s in self._slicesigs:
s._clear()
def _update(self):
val, next = self._val, self._next
@ -278,7 +281,10 @@ class _Signal(object):
### use call interface for shadow signals ###
def __call__(self, left, right=None):
return _SliceSignal(self, left, right)
s = _SliceSignal(self, left, right)
self._slicesigs.append(s)
return s
### operators for which delegation to current value is appropriate ###

2
myhdl/_extractHierarchy.py
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@ -158,7 +158,7 @@ class _HierExtr(object):
sys.setprofile(None)
if not hierarchy:
raise ExtractHierarchyError(_error.NoInstances)
self.top = _top
# streamline hierarchy

8
myhdl/conversion/_analyze.py
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@ -44,6 +44,7 @@ from myhdl.conversion._misc import (_error, _access, _kind, _context,
_ConversionMixin, _Label, _genUniqueSuffix)
from myhdl._extractHierarchy import _isMem, _UserCode
from myhdl._Signal import _Signal, _WaiterList
from myhdl._ShadowSignal import _SliceSignal
from myhdl._util import _isTupleOfInts, _dedent
myhdlObjects = myhdl.__dict__.values()
@ -95,9 +96,14 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
for n, s in sigdict.items():
if s._name is not None:
continue
if isinstance(s, _SliceSignal):
continue
s._name = _makeName(n, prefixes)
if not s._nrbits:
raise ConversionError(_error.UndefinedBitWidth, s._name)
# slice signals
for sl in s._slicesigs:
sl._setName(hdl)
siglist.append(s)
# list of signals
for n, m in memdict.items():
@ -1618,6 +1624,8 @@ class _AnalyzeBlockVisitor(_AnalyzeVisitor):
for n in self.tree.inputs:
s = self.tree.sigdict[n]
s._read = True
if isinstance(s, _SliceSignal):
s._sig.read = True
# def visitReturn(self, node, *args):
# ### value should be None

7
myhdl/conversion/_toVHDL.py
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@ -155,9 +155,10 @@ class _ToVHDLConvertor(object):
# clean up signal names
for sig in siglist:
sig._name = None
sig._driven = False
sig._read = False
sig._clear()
# sig._name = None
# sig._driven = False
# sig._read = False
# clean up attributes
self.name = None

7
myhdl/conversion/_toVerilog.py
View File

@ -135,9 +135,10 @@ class _ToVerilogConvertor(object):
# clean up signal names
for sig in siglist:
sig._name = None
sig._driven = False
sig._read = False
sig._clear()
# sig._name = None
# sig._driven = False
# sig._read = False
# clean up attributes
self.name = None