implmented SliceSignal conversion through slice/index names directly

myhdl/_ShadowSignal.py

@@ -39,7 +39,7 @@ class _ShadowSignal(_Signal):
 
     def __init__(self, val):
         _Signal.__init__(self, val)
-        self.driven = True
+        self._driven = True
 
     # remove next attribute assignment
     next = property(_Signal._get_next, None, None, "'next' access methods")
@@ -60,36 +60,48 @@ class _SliceSignal(_ShadowSignal):
         self._left = left
         self._right = right
         if right is None:
-            gen = self.genfuncIndex()
+            gen = self._genfuncIndex()
         else:
-            gen = self.genfuncSlice()
+            gen = self._genfuncSlice()
         self._waiter = _SignalWaiter(gen)
 
-    def genfuncIndex(self):
+    def _genfuncIndex(self):
         sig, index = self._sig, self._left
         set_next = _ShadowSignal._set_next
         while 1:
             set_next(self, sig[index])
             yield sig
 
-    def genfuncSlice(self):
+    def _genfuncSlice(self):
         sig, left, right = self._sig, self._left, self._right
         set_next = _Signal._set_next
         while 1:
             set_next(self, sig[left:right])
             yield sig
 
-    def toVerilog(self):
+    def _setName(self, hdl):
         if self._right is None:       
-            return "assign %s = %s[%s];" % (self._name, self._sig._name, self._left)
+            if hdl == 'Verilog':
+                self._name = "%s[%s]" % (self._sig._name, self._left)
             else:
-            return "assign %s = %s[%s-1:%s];" % (self._name, self._sig._name, self._left, self._right)
+                self._name = "%s(%s)" % (self._sig._name, self._left)
+        else:
+            if hdl == 'Verilog':
+                self._name = "%s[%s-1:%s]" % (self._sig._name, self._left, self._right)
+            else:
+                self._name = "%s(%s-1 downto %s)" % (self._sig._name, self._left, self._right)
 
-    def toVHDL(self):
+#     def toVerilog(self):
-        if self._right is None:
+#         if self._right is None:
-            return "%s <= %s(%s);" % (self._name, self._sig._name, self._left)
+#             return "assign %s = %s[%s];" % (self._name, self._sig._name, self._left)
-        else:
+#         else:
-            return "%s <= %s(%s-1 downto %s);" % (self._name, self._sig._name, self._left, self._right)
+#             return "assign %s = %s[%s-1:%s];" % (self._name, self._sig._name, self._left, self._right)
+
+#     def toVHDL(self):
+#         if self._right is None:
+#             return "%s <= %s(%s);" % (self._name, self._sig._name, self._left)
+#         else:
+#             return "%s <= %s(%s-1 downto %s);" % (self._name, self._sig._name, self._left, self._right)
 
 
 

myhdl/_Signal.py

@@ -105,7 +105,7 @@ class _Signal(object):
                  '_eventWaiters', '_posedgeWaiters', '_negedgeWaiters',
                  '_code', '_tracing', '_nrbits', '_checkVal', '_setNextVal',
                  '_printVcd', '_driven' ,'_read', '_name', '_used', '_inList',
-                 '_waiter', 'toVHDL', 'toVerilog'
+                 '_waiter', 'toVHDL', 'toVerilog', '_slicesigs'
                 )
 
 
@@ -152,6 +152,7 @@ class _Signal(object):
         self._posedgeWaiters = _PosedgeWaiterList(self)
         self._negedgeWaiters = _NegedgeWaiterList(self)
         self._code = ""
+        self._slicesigs = []
         self._tracing = 0
         _signals.append(self)
 
@@ -161,6 +162,8 @@ class _Signal(object):
         del self._negedgeWaiters[:]
         self._next = self._val = self._init
         self._name = self._read = self._driven = None
+        for s in self._slicesigs:
+            s._clear()
         
     def _update(self):
         val, next = self._val, self._next
@@ -278,7 +281,10 @@ class _Signal(object):
 
     ### use call interface for shadow signals ###
     def __call__(self, left, right=None):
-        return _SliceSignal(self, left, right)
+        s = _SliceSignal(self, left, right)
+        self._slicesigs.append(s)
+        return s
+
 
     ### operators for which delegation to current value is appropriate ###
         

myhdl/conversion/_analyze.py

@@ -44,6 +44,7 @@ from myhdl.conversion._misc import (_error, _access, _kind, _context,
                                     _ConversionMixin, _Label, _genUniqueSuffix)
 from myhdl._extractHierarchy import _isMem, _UserCode
 from myhdl._Signal import _Signal, _WaiterList
+from myhdl._ShadowSignal import _SliceSignal
 from myhdl._util import _isTupleOfInts, _dedent
 
 myhdlObjects = myhdl.__dict__.values()
@@ -95,9 +96,14 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
         for n, s in sigdict.items():
             if s._name is not None:
                 continue
+            if isinstance(s, _SliceSignal):
+                continue
             s._name = _makeName(n, prefixes)
             if not s._nrbits:
                 raise ConversionError(_error.UndefinedBitWidth, s._name)
+            # slice signals
+            for sl in s._slicesigs:
+                sl._setName(hdl)
             siglist.append(s)
         # list of signals
         for n, m in memdict.items():
@@ -1618,6 +1624,8 @@ class _AnalyzeBlockVisitor(_AnalyzeVisitor):
         for n in self.tree.inputs:
             s = self.tree.sigdict[n]
             s._read = True
+            if isinstance(s, _SliceSignal):
+                s._sig.read = True
             
 #     def visitReturn(self, node, *args):
 #         ### value should be None

myhdl/conversion/_toVHDL.py

@@ -155,9 +155,10 @@ class _ToVHDLConvertor(object):
         
         # clean up signal names
         for sig in siglist:
-            sig._name = None
+            sig._clear()
-            sig._driven = False
+#             sig._name = None
-            sig._read = False
+#             sig._driven = False
+#             sig._read = False
             
         # clean up attributes
         self.name = None

myhdl/conversion/_toVerilog.py

@@ -135,9 +135,10 @@ class _ToVerilogConvertor(object):
 
         # clean up signal names
         for sig in siglist:
-            sig._name = None
+            sig._clear()
-            sig._driven = False
+#             sig._name = None
-            sig._read = False
+#             sig._driven = False
+#             sig._read = False
             
         # clean up attributes
         self.name = None