Added test with list of sigs in sensitivity list.

This also required a correction of list bracket syntax in VHDL.

myhdl/conversion/_analyze.py

@@ -65,11 +65,14 @@ def _makeName(n, prefixes):
 ##     print name
     return name
                     
-def _analyzeSigs(hierarchy):
+def _analyzeSigs(hierarchy, hdl='Verilog'):
     curlevel = 0
     siglist = []
     memlist = []
     prefixes = []
+    open, close = '[', ']'
+    if hdl == 'VHDL':
+        open, close = '(', ')'
     
     for inst in hierarchy:
         level = inst.level
@@ -100,7 +103,7 @@ def _analyzeSigs(hierarchy):
             memlist.append(m)
 
     # handle the case where a named signal appears in a list also; such a list
-    # is not declared and references to it in a generator will be flagged as an error 
+    # is not declared and references to it in a generator will be flagged as an error
     for m in memlist:
         for s in m.mem:
             if s._name is not None:
@@ -109,7 +112,7 @@ def _analyzeSigs(hierarchy):
         if not m.decl:
             continue
         for i, s in enumerate(m.mem):
-            s._name = "%s[%s]" % (m.name, i)
+            s._name = "%s%s%s%s" % (m.name, open, i, close)
             if not s._nrbits:
                 raise ConversionError(_error.UndefinedBitWidth, s._name)
             if type(s.val) != type(m.elObj.val):

myhdl/conversion/_toVHDL.py

@@ -120,7 +120,7 @@ class _ToVHDLConvertor(object):
         if not os.path.isfile(ppath):
             pfile = open(ppath, 'w')
 
-        siglist, memlist = _analyzeSigs(h.hierarchy)
+        siglist, memlist = _analyzeSigs(h.hierarchy, hdl='VHDL')
         arglist = _flatten(h.top)
         # print h.top
         _checkArgs(arglist)

myhdl/test/conversion/general/test_listofsigs.py

@@ -0,0 +1,88 @@
+from myhdl import *
+
+
+def intbv2list():
+    """Conversion between intbv and list of boolean signals."""
+    
+    N = 8
+    M= 2**N
+    a = Signal(intbv(0)[N:])
+    b = [Signal(bool(0)) for i in range(len(a))]
+    z = Signal(intbv(0)[N:])
+
+    @always(a)
+    def extract():
+        for i in range(len(a)):
+            b[i].next = a[i]
+
+    @always(*b)
+    def assemble():
+        for i in range(len(b)):
+            z.next[i] = b[i]
+
+    @instance
+    def stimulus():
+        for i in range(M):
+            a.next = i
+            yield delay(10)
+            assert z == a
+            print a
+        raise StopSimulation
+
+    return extract, assemble, stimulus
+            
+    
+def test_intbv2list():
+    assert conversion.verify(intbv2list) == 0
+
+def inv(z, a):
+    @always_comb
+    def logic():
+        z.next = not a
+    return logic
+    
+def processlist():
+    """Extract list from intbv, do some processing, reassemble."""
+    
+    N = 8
+    M= 2**N
+    a = Signal(intbv(0)[N:])
+    b = [Signal(bool(0)) for i in range(len(a))]
+    c = [Signal(bool(0)) for i in range(len(a))]
+    z = Signal(intbv(0)[N:])
+
+    @always(a)
+    def extract():
+        for i in range(len(a)):
+            b[i].next = a[i]
+
+    inst = [None] * len(b)
+    for i in range(len(b)):
+        inst[i] = inv(c[i], b[i])
+
+    @always(*c)
+    def assemble():
+        for i in range(len(c)):
+            z.next[i] = c[i]
+
+    @instance
+    def stimulus():
+        for i in range(M):
+            a.next = i
+            yield delay(10)
+            assert z == ~a
+            print z
+        raise StopSimulation
+
+    return extract, inst, assemble, stimulus
+            
+    
+## def test_processlist():
+##     # Simulation(processlist()).run()
+##     assert conversion.verify(processlist) == 0
+
+
+
+        
+
+