partial

myhdl/test/toVerilog/test_bin2gray.py

@@ -7,7 +7,7 @@ from myhdl import *
 
 from util import setupCosimulation
 
-def bin2gray(B, G, width):
+def bin2gray2(B, G, width):
     """ Gray encoder.
 
     B -- input intbv signal, binary encoded
@@ -21,21 +21,24 @@ def bin2gray(B, G, width):
         for i in range(width):
             G.next[i] = Bext[i+1] ^ Bext[i]
 
-def bin2gray2(B, G, width):
+def bin2gray(B, G, width):
+    
     """ Gray encoder.
 
     B -- input intbv signal, binary encoded
     G -- output intbv signal, gray encoded
     width -- bit width
+    
     """
 
+    @always_comb
     def logic():
         Bext = intbv(0)[width+1:]
         Bext[:] = B
         for i in range(width):
             G.next[i] = Bext[i+1] ^ Bext[i]
 
-    return always_comb(logic)
+    return logic
            
             
 objfile = "bin2gray.o"           

myhdl/test/toVerilog/test_inc.py

@@ -30,6 +30,7 @@ def incRef(count, enable, clock, reset, n):
                 count.next = (count + 1) % n
                 
 def inc(count, enable, clock, reset, n):
+    
     """ Incrementer with enable.
     
     count -- output
@@ -37,7 +38,9 @@ def inc(count, enable, clock, reset, n):
     clock -- clock input
     reset -- asynchronous reset input
     n -- counter max value
+    
     """
+    
     @always(clock.posedge, reset.negedge)
     def incProcess():
         if reset == ACTIVE_LOW:
@@ -45,6 +48,7 @@ def inc(count, enable, clock, reset, n):
         else:
             if enable:
                 count.next = (count + 1) % n
+                
     return incProcess
 
 def inc2(count, enable, clock, reset, n):