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https://github.com/myhdl/myhdl.git
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user-defined verilog
bug fixes with hierarchical naming
This commit is contained in:
jand
parent
28258b40ff
commit
26a43394c4
@ -191,6 +191,14 @@ class Signal(object):
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return self._min
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min = property(_get_min, None)
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# support for the 'driven' attribute
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def _get_driven(self):
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return self._driven
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def _set_driven(self, val):
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assert val in ("reg", "wire")
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self._driven = val
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driven = property(_get_driven, _set_driven, None, "'driven' access methods")
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# set next methods
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def _setNextBool(self, val):
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if not val in (0, 1):
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@ -399,7 +407,10 @@ class Signal(object):
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# representation
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def __str__(self):
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return str(self._val)
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if self._name:
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return self._name
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else:
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return str(self._val)
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def __repr__(self):
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return "Signal(" + repr(self._val) + ")"
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@ -221,6 +221,8 @@ def _checkArgs(arglist):
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waiters.append(_SignalTupleWaiter(cosim._waiter()))
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elif isinstance(arg, _Waiter):
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waiters.append(arg)
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elif arg == True:
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pass
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else:
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raise SimulationError(_error.ArgType, str(type(arg)))
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if id(arg) in ids:
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@ -48,7 +48,7 @@ __author__ = "Jan Decaluwe <jan@jandecaluwe.com>"
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__revision__ = "$Revision$"
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__date__ = "$Date$"
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__version__ = "0.5dev3"
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__version__ = "0.5dev4"
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import warnings
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@ -48,8 +48,6 @@ class _error:
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pass
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_error.NoInstances = "No instances found"
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_filelinemap = {}
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_memInfoMap = {}
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class _MemInfo(object):
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@ -74,6 +72,24 @@ def _makeMemInfo(mem):
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def _isMem(mem):
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return id(mem) in _memInfoMap
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_customVerilogMap = {}
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class _CustomVerilog(object):
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__slots__ = ['code', 'namespace']
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def __init__(self, code, namespace):
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self.code = code
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self.namespace = namespace
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def __str__(self):
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code = self.code % self.namespace
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code = "\n%s\n" % code
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return code
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def _addCustomVerilog(arg, code, namespace):
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assert id(arg) not in _customVerilogMap
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_customVerilogMap[id(arg)] = _CustomVerilog(code, namespace)
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def _isListOfSigs(obj):
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if obj and isinstance(obj, list):
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for e in obj:
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@ -106,7 +122,8 @@ class _HierExtr(object):
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global _profileFunc
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global _memInfoMap
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_memInfoMap = {}
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self.skipNames = ('always_comb', 'always', '_always_decorator', 'instances', 'processes', 'posedge', 'negedge')
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self.skipNames = ('always_comb', 'always', '_always_decorator', \
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'instances', 'processes', 'posedge', 'negedge')
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self.skip = 0
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self.hierarchy = hierarchy = []
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self.absnames = absnames = {}
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@ -139,8 +156,11 @@ class _HierExtr(object):
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# streamline hierarchy
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hierarchy.reverse()
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## from pprint import pprint
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## pprint(hierarchy)
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# print hierarchy
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# walk the hierarchy to define relative and absolute names
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# in this case, we'll use the names from the lowest levels
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# use names as high as possible in hierarchy to avoid ambiguity
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names = {}
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obj, subs = hierarchy[0][1]
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names[id(obj)] = name
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@ -150,13 +170,16 @@ class _HierExtr(object):
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assert id(obj) in names
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tn = absnames[id(obj)]
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for sn, so in subs:
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names[id(so)] = sn
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if not id(so) in names:
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names[id(so)] = sn
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absnames[id(so)] = "%s_%s" % (tn, sn)
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if isinstance(so, (tuple, list)):
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for i, soi in enumerate(so):
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names[id(soi)] = "%s[%s]" % (sn, i)
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if not(id(soi)) in names:
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names[id(soi)] = "%s_%s" % (sn, i)
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absnames[id(soi)] = "%s_%s_%s" % (tn, sn, i)
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m[1] = names[id(obj)]
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## pprint(hierarchy)
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@ -172,8 +195,16 @@ class _HierExtr(object):
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elif event == "return":
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if not self.skip:
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if _isGenSeq(arg):
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if not self.skip:
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isGenSeq = _isGenSeq(arg)
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if isGenSeq:
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if "__verilog__" in frame.f_locals:
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code = frame.f_locals["__verilog__"]
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namespace = frame.f_globals.copy()
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namespace.update(frame.f_locals)
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_addCustomVerilog(arg, code, namespace)
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# building hierarchy only makes sense if there are generators
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if isGenSeq and arg:
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sigdict = {}
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memdict = {}
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for dict in (frame.f_globals, frame.f_locals):
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@ -215,9 +246,9 @@ class _HierExtr(object):
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self.hierarchy.append(inst)
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self.level -= 1
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func_name = frame.f_code.co_name
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if func_name in self.skipNames:
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self.skip = 0
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func_name = frame.f_code.co_name
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if func_name in self.skipNames:
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self.skip = 0
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@ -37,8 +37,8 @@ def _isGenSeq(obj):
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return True
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if not isinstance(obj, (ListType, TupleType, Set)):
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return False
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if not obj:
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return False
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## if not obj:
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## return False
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for e in obj:
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if not _isGenSeq(e):
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return False
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@ -43,7 +43,7 @@ from myhdl._always_comb import _AlwaysComb
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from myhdl._always import _Always
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from myhdl._toVerilog import _error, _access, _kind, _context, \
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_ToVerilogMixin, _Label
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from myhdl._extractHierarchy import _isMem
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from myhdl._extractHierarchy import _isMem, _CustomVerilog
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myhdlObjects = myhdl.__dict__.values()
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builtinObjects = __builtin__.__dict__.values()
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@ -74,14 +74,19 @@ def _analyzeSigs(hierarchy):
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delta = curlevel - level
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curlevel = level
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assert(delta >= -1)
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#print
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#print curlevel
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#print delta
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#print prefixes
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if delta == -1:
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prefixes.append(name)
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elif delta == 0:
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prefixes.pop()
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prefixes.append(name)
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else:
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prefixes = prefixes[:curlevel]
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prefixes = prefixes[:curlevel-1]
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prefixes.append(name)
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assert prefixes[-1] == name
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#print prefixes
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# signals
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#print sigdict
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for n, s in sigdict.items():
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if s._name is not None:
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continue
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@ -125,7 +130,9 @@ def _analyzeSigs(hierarchy):
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def _analyzeGens(top, absnames):
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genlist = []
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for g in top:
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if isinstance(g, (_AlwaysComb, _Always)):
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if isinstance(g, _CustomVerilog):
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ast = g
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elif isinstance(g, (_AlwaysComb, _Always)):
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f = g.func
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s = inspect.getsource(f)
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# remove decorators
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@ -38,8 +38,9 @@ import warnings
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import myhdl
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from myhdl import *
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from myhdl import ToVerilogError, ToVerilogWarning
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from myhdl._extractHierarchy import _HierExtr, _isMem, _getMemInfo
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from myhdl._util import _flatten
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from myhdl._extractHierarchy import _HierExtr, _isMem, _getMemInfo, \
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_CustomVerilog, _customVerilogMap
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from myhdl._always_comb import _AlwaysComb
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from myhdl._always import _Always
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from myhdl._toVerilog import _error, _access, _kind,_context, \
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@ -52,9 +53,21 @@ _profileFunc = None
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def _checkArgs(arglist):
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for arg in arglist:
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if not type(arg) in (GeneratorType, _AlwaysComb, _Always):
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if not type(arg) in (GeneratorType, _AlwaysComb, _Always, _CustomVerilog):
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raise ToVerilogError(_error.ArgType, arg)
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def _flatten(*args):
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arglist = []
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for arg in args:
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if id(arg) in _customVerilogMap:
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arglist.append(_customVerilogMap[id(arg)])
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elif isinstance(arg, (list, tuple, Set)):
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for item in arg:
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arglist.extend(_flatten(item))
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else:
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arglist.append(arg)
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return arglist
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class _ToVerilogConvertor(object):
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@ -93,6 +106,7 @@ class _ToVerilogConvertor(object):
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siglist, memlist = _analyzeSigs(h.hierarchy)
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arglist = _flatten(h.top)
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# print h.top
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_checkArgs(arglist)
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genlist = _analyzeGens(arglist, h.absnames)
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intf = _analyzeTopFunc(func, *args, **kwargs)
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@ -239,6 +253,9 @@ def _convertGens(genlist, vfile):
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blockBuf = StringIO()
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funcBuf = StringIO()
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for ast in genlist:
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if isinstance(ast, _CustomVerilog):
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blockBuf.write(str(ast))
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continue
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if ast.kind == _kind.ALWAYS:
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Visitor = _ConvertAlwaysVisitor
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elif ast.kind == _kind.INITIAL:
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@ -61,9 +61,9 @@ class SigTest(TestCase):
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self.negedgeWaiters = [object() for i in range(7)]
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def testPublicInterface(self):
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""" public interface of a sig: val, next, posedge, negedge, min, max"""
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""" public interface of a sig: val, next, posedge, negedge, min, max, driven"""
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s1 = Signal(1)
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expected = ['next', 'val', 'posedge', 'negedge', 'min', 'max']
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expected = ['next', 'val', 'posedge', 'negedge', 'min', 'max', 'driven']
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iface = [attr for attr in dir(s1) if attr[0] != '_']
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expected.sort()
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iface.sort()
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77
myhdl/test/toVerilog/test_bugreports.py
Normal file
77
myhdl/test/toVerilog/test_bugreports.py
Normal file
@ -0,0 +1,77 @@
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from myhdl import *
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from util import verilogCompile
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#############################
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# bug report (Tom Dillon)
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# conflicts in reg/wire names
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#############################
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width = 8
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def add(x,a,b) :
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def logic() :
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x.next = a + b
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L0 = always_comb(logic)
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return L0
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def add3(x,a,b,c) :
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x0 = Signal(intbv(0,min=-2**(width-1),max=2**(width-1)))
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A0 = add(x0,a,b)
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A1 = add(x,x0,c)
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return instances()
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def TestModule(x,a,b,c,d,e) :
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x0 = Signal(intbv(0,min=-2**(width-1),max=2**(width-1)))
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A0 = add3(x0,a,b,c)
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A1 = add3(x,x0,d,e)
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return instances()
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x,a,b,c,d,e = [Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) for i in range(6)]
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toVerilog(TestModule, x,a,b,c,d,e)
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verilogCompile(TestModule.func_name)
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##############################
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# Bug report (Tom Dillon)
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# Conflicts in reg/wire names
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###############################
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def add(x,a,b) :
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def logic() :
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x.next = a + b
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L0 = always_comb(logic)
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return L0
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def add4(x,a,b,c,d) :
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xL = [Signal(intbv(0,min=-2**(width+2),max=2**(width+2))) for i in range(2)]
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#xl0 = Signal(intbv(0,min=-2**(width+2),max=2**(width+2)))
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#xl1 = Signal(intbv(0,min=-2**(width+2),max=2**(width+2)))
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A0 = add(xL[0],a,b)
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A1 = add(xL[1],xL[0],c)
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A2 = add(x, xL[1],d)
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return instances()
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def TestModule(x,a,b,c,d,e):
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x0 = Signal(intbv(0,min=-2**(width+2),max=2**(width+2)))
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A0 = add4(x0,a,b,c,d)
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A1 = add4(x,x0,e,a,b)
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return instances()
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width = 8
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x,a,b,c,d,e = [Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) for i in range(6)]
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toVerilog(TestModule, x,a,b,c,d,e)
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verilogCompile(TestModule.func_name)
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@ -21,6 +21,12 @@ def setupCosimulationCver(**kwargs):
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"%s.v tb_%s.v " % (name, name)
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return Cosimulation(cmd, **kwargs)
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def verilogCompileCver(name):
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cmd = "cver -c %s.v" % name
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os.system(cmd)
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setupCosimulation = setupCosimulationIcarus
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setupCosimulation = setupCosimulationCver
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verilogCompile = verilogCompileCver
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