Added missing visit_NameConnstant() for Python versions 3.7 adn 3.8 (#380)

Modified test

myhdl/conversion/_toVerilog.py

@@ -1651,6 +1651,9 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
         def visit_Str(self, node):
             node.signed = False
 
+        def visit_NameConstant(self, node):
+            node.signed = False
+
     def visit_Name(self, node):
         if isinstance(node.ctx, ast.Store):
             self.setName(node)

myhdl/test/conversion/general/test_dec.py

@@ -9,6 +9,7 @@ from myhdl import *
 
 ACTIVE_LOW, INACTIVE_HIGH = 0, 1
 
+
 @block
 def decRef(count, enable, clock, reset, n):
     """ Decrementer with enable.
@@ -19,6 +20,7 @@ def decRef(count, enable, clock, reset, n):
     reset -- asynchronous reset input
     n -- counter max value
     """
+
     @instance
     def logic():
         while 1:
@@ -31,6 +33,7 @@ def decRef(count, enable, clock, reset, n):
                         count.next = n - 1
                     else:
                         count.next = count - 1
+
     return logic
 
 
@@ -44,6 +47,7 @@ def dec(count, enable, clock, reset, n):
     reset -- asynchronous reset input
     n -- counter max value
     """
+
     @instance
     def decProcess():
         while 1:
@@ -51,11 +55,12 @@ def dec(count, enable, clock, reset, n):
             if reset == ACTIVE_LOW:
                 count.next = 0
             else:
-                if enable:
+                if enable == True:
                     if count == -n:
                         count.next = n - 1
                     else:
                         count.next = count - 1
+
     return decProcess
 
 
@@ -150,6 +155,7 @@ def DecBench(dec):
             clock.next = not clock
 
     enables = tuple([min(1, randrange(5)) for i in range(1000)])
+
     @instance
     def stimulus():
         reset.next = INACTIVE_HIGH
@@ -183,16 +189,18 @@ def DecBench(dec):
 def testDecRef():
     assert DecBench(decRef).verify_convert() == 0
 
+
 def testDec():
     assert DecBench(dec).verify_convert() == 0
 
+
 def testDecFunc():
     assert DecBench(decFunc).verify_convert() == 0
 
+
 def testDecTask():
     assert DecBench(decTask).verify_convert() == 0
 
-
 # # def testDecTaskFreeVar():
 # #     assert verify(DecBench, decTaskFreeVar) == 0