From 2799d579f179b89aa0b3b6d79e1f797d5570d108 Mon Sep 17 00:00:00 2001
From: jand <none@none>
Date: Mon, 2 Feb 2004 21:47:49 +0000
Subject: [PATCH] intro

---
 doc/manual/MyHDL.tex          | 20 ++++++++++++--------
 doc/whatsnew04/whatsnew04.tex |  2 +-
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/doc/manual/MyHDL.tex b/doc/manual/MyHDL.tex
index 6af10778..9280f7fe 100644
--- a/doc/manual/MyHDL.tex
+++ b/doc/manual/MyHDL.tex
@@ -35,13 +35,13 @@ that returns generators. With this approach, \myhdl{} directly supports
 features such as named port association, arrays of instances, and
 conditional instantiation. 
 
-\myhdl{} supports the classic hardware description concepts.  It provides
-a signal class similar to the VHDL signal, a class for bit oriented
-operations, and support for enumeration types.  The Python
-\code{yield} statement is used as a general sensitivity list to
-wait on a signal change, an edge, a delay, or on another
-generator. \myhdl{} supports waveform viewing by tracing signal changes
-in a VCD file.
+\myhdl{} supports the classic hardware description concepts.  It
+provides a signal class similar to the VHDL signal, a class for bit
+oriented operations, and support for enumeration types.  The Python
+\code{yield} statement is used as a general sensitivity list to wait
+on a signal change, an edge, a delay, or on the completion of another
+generator. \myhdl{} supports waveform viewing by tracing signal
+changes in a VCD file.
 
 Python's rare combination of power and clarity makes it ideal for high
 level modeling.  It can be expected that \myhdl{} users will often
@@ -55,6 +55,10 @@ VHDL and Verilog designs, by co-simulation with any simulator that has
 a PLI.  The distribution contains a PLI module for the
 Icarus Verilog simulator.
 
+Finally, a subset of \myhdl{} code can be converted automatically into
+synthesizable Verilog code. This feature provides a direct path from
+Python to an FPGA or ASIC implementation.
+
 The \myhdl{} software is open source software. It is licensed under the
 GNU Lesser General Public License (LGPL).
 
@@ -71,7 +75,7 @@ GNU Lesser General Public License (LGPL).
 \input{unittest.tex}
 \input{cosimulation.tex}
 
-\chapter{Conversion to Verilog for implementation \label{conversion}}
+\chapter{Conversion to Verilog\label{conversion}}
 \input{conversion.tex}
 
 \input{reference.tex}
diff --git a/doc/whatsnew04/whatsnew04.tex b/doc/whatsnew04/whatsnew04.tex
index d056f110..e7023901 100644
--- a/doc/whatsnew04/whatsnew04.tex
+++ b/doc/whatsnew04/whatsnew04.tex
@@ -7,7 +7,7 @@
 \usepackage{graphicx}
 % $Id$
 
-\title{New in \myhdl\ 0.4: Verilog conversion for implementation}
+\title{New in \myhdl\ 0.4: Conversion to Verilog}
 \release{0.4}
 \author{Jan Decaluwe}
 \authoraddress{\email{jan@jandecaluwe.com}}