Added yet more support to avoid explicit val attr on sigs

Assigning sigs to items/slices of intbvs comes for free ...

doc/informal.tex

@@ -250,7 +250,7 @@ def bin2gray(width, B, G):
     while 1:
         yield B
         for i in range(width):
-            G.next[i] = B.val[i+1] ^ B.val[i]
+            G.next[i] = B[i+1] ^ B[i]
 
 \end{verbatim}
 
@@ -285,7 +285,7 @@ def testBench(width):
         for i in range(2**width):
             B.next = intbv(i)
             yield delay(10)
-            print "B: " + bin(B.val, width) + "| G: " + bin(G.val, width)
+            print "B: " + bin(B, width) + "| G: " + bin(G, width)
 
     return (dut, stimulus())
 

example/arith_lib/Dec.py

@@ -18,7 +18,7 @@ def Dec(width, speed, A, Z, architecture=BEHAVIOR):
     def Behavioral():
         while 1:
             yield A
-            Z.next = A.val - 1
+            Z.next = A - 1
 
     def Structural():
         AI = Signal(intbv())
@@ -27,8 +27,8 @@ def Dec(width, speed, A, Z, architecture=BEHAVIOR):
         def logic():
             while 1:
                 yield A, PO
-                AI.next = ~A.val
-                Z.next = A.val ^ intbv.concat(PO.val[width-1:], '1')
+                AI.next = ~A
+                Z.next = A ^ intbv.concat(PO[width-1:], '1')
         return [prefix, logic()]
 
     if architecture == BEHAVIOR:

example/arith_lib/PrefixAnd.py

@@ -14,7 +14,7 @@ def PrefixAnd(width, speed, PI, PO):
         PT = Signal(intbv())
         while 1:
             yield PI, PT
-            PT.next[n:] = PI.val
+            PT.next[n:] = PI
             for l in range(1, m+1):
                 for k in range(2**(m-l)):
                     for i in range(2**(l-1)):
@@ -34,7 +34,7 @@ def PrefixAnd(width, speed, PI, PO):
             PT.next[0] = PI[0]
             for i in range(1, n):
                 PT.next[i] = PI[i] & PT[i-1]
-            PO.next = PT.val
+            PO.next = PT
 
     if speed == SLOW:
         return slowPrefix()

example/rs232/rs232_rx.py

@@ -23,7 +23,7 @@ def rs232_rx(rx, actual, cfg):
     data[7] = 0
     for i in downrange(cfg.n_bits):
         yield delay(period)
-        data[i] = rx.val
+        data[i] = rx
         
     if cfg.parity is not None:
         yield delay(period)

myhdl/Signal.py

@@ -114,6 +114,8 @@ class Signal(object):
         _siglist.append(self)
         return self._next
     def _set_next(self, val):
+        if isinstance(val, Signal):
+            val = val._val
         if not isinstance(val, self._type):
             raise TypeError, "Incompatible type(v) for sig.next = v\n" \
                   "           Expected %s, got %s" % (self._type, type(val))