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Added yet more support to avoid explicit val attr on sigs

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Assigning sigs to items/slices of intbvs comes for free ...
This commit is contained in:
jand 2003-02-16 21:36:58 +00:00
parent 589617ecae
commit 283882d29b
5 changed files with 10 additions and 8 deletions
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4
doc/informal.tex
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@ -250,7 +250,7 @@ def bin2gray(width, B, G):
while 1: while 1:
yield B yield B
for i in range(width): for i in range(width):
G.next[i] = B.val[i+1] ^ B.val[i] G.next[i] = B[i+1] ^ B[i]
\end{verbatim} \end{verbatim}
@ -285,7 +285,7 @@ def testBench(width):
for i in range(2**width): for i in range(2**width):
B.next = intbv(i) B.next = intbv(i)
yield delay(10) yield delay(10)
print "B: " + bin(B.val, width) + "| G: " + bin(G.val, width) print "B: " + bin(B, width) + "| G: " + bin(G, width)
return (dut, stimulus()) return (dut, stimulus())

6
example/arith_lib/Dec.py
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@ -18,7 +18,7 @@ def Dec(width, speed, A, Z, architecture=BEHAVIOR):
def Behavioral(): def Behavioral():
while 1: while 1:
yield A yield A
Z.next = A.val - 1 Z.next = A - 1
def Structural(): def Structural():
AI = Signal(intbv()) AI = Signal(intbv())
@ -27,8 +27,8 @@ def Dec(width, speed, A, Z, architecture=BEHAVIOR):
def logic(): def logic():
while 1: while 1:
yield A, PO yield A, PO
AI.next = ~A.val AI.next = ~A
Z.next = A.val ^ intbv.concat(PO.val[width-1:], '1') Z.next = A ^ intbv.concat(PO[width-1:], '1')
return [prefix, logic()] return [prefix, logic()]
if architecture == BEHAVIOR: if architecture == BEHAVIOR:

4
example/arith_lib/PrefixAnd.py
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@ -14,7 +14,7 @@ def PrefixAnd(width, speed, PI, PO):
PT = Signal(intbv()) PT = Signal(intbv())
while 1: while 1:
yield PI, PT yield PI, PT
PT.next[n:] = PI.val PT.next[n:] = PI
for l in range(1, m+1): for l in range(1, m+1):
for k in range(2**(m-l)): for k in range(2**(m-l)):
for i in range(2**(l-1)): for i in range(2**(l-1)):
@ -34,7 +34,7 @@ def PrefixAnd(width, speed, PI, PO):
PT.next[0] = PI[0] PT.next[0] = PI[0]
for i in range(1, n): for i in range(1, n):
PT.next[i] = PI[i] & PT[i-1] PT.next[i] = PI[i] & PT[i-1]
PO.next = PT.val PO.next = PT
if speed == SLOW: if speed == SLOW:
return slowPrefix() return slowPrefix()

2
example/rs232/rs232_rx.py
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@ -23,7 +23,7 @@ def rs232_rx(rx, actual, cfg):
data[7] = 0 data[7] = 0
for i in downrange(cfg.n_bits): for i in downrange(cfg.n_bits):
yield delay(period) yield delay(period)
data[i] = rx.val data[i] = rx
if cfg.parity is not None: if cfg.parity is not None:
yield delay(period) yield delay(period)

2
myhdl/Signal.py
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@ -114,6 +114,8 @@ class Signal(object):
_siglist.append(self) _siglist.append(self)
return self._next return self._next
def _set_next(self, val): def _set_next(self, val):
if isinstance(val, Signal):
val = val._val
if not isinstance(val, self._type): if not isinstance(val, self._type):
raise TypeError, "Incompatible type(v) for sig.next = v\n" \ raise TypeError, "Incompatible type(v) for sig.next = v\n" \
" Expected %s, got %s" % (self._type, type(val)) " Expected %s, got %s" % (self._type, type(val))