Merge pull request #200 from hgomersall/initial_value_support

[FIX] fixed initial value support for bool lists and list of wires

myhdl/conversion/_toVHDL.py

@@ -468,9 +468,14 @@ def _writeSigDecls(f, intf, siglist, memlist):
             sig_vhdl_objs = [inferVhdlObj(each) for each in m.mem]
 
             if all([each._init == m.mem[0]._init for each in m.mem]):
-                val_str = (
-                    ' := (others => %dX"%s")' %
-                    (sig_vhdl_objs[0].size, str(m.mem[0]._init)))
+                if isinstance(m.mem[0]._init, bool):
+                    val_str = (
+                        ' := (others => \'%s\')' % str(int(m.mem[0]._init)))
+
+                else:
+                    val_str = (
+                        ' := (others => %dX"%s")' %
+                        (sig_vhdl_objs[0].size, str(m.mem[0]._init)))
             else:
                 _val_str = ',\n    '.join(
                     ['%dX"%s"' % (obj.size, str(each._init)) for

myhdl/conversion/_toVerilog.py

@@ -368,7 +368,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
         if m._driven:
             k = m._driven
 
-            if toVerilog.initial_values:
+            if toVerilog.initial_values and not k == 'wire':
                 if all([each._init == m.mem[0]._init for each in m.mem]):
 
                     initialize_block_name = ('INITIALIZE_' + m.name).upper()

myhdl/test/conversion/general/test_initial_values.py

@@ -47,6 +47,24 @@ def initial_value_enum_bench(initial_val, **kwargs):
 
     return state_walker, clkgen
 
+@block
+def bool_writer(signal, clk):
+
+    @always(clk.posedge)
+    def writer():
+        print(int(signal))
+
+    return writer
+
+@block
+def int_writer(signal, clk):
+
+    @always(clk.posedge)
+    def writer():
+        print(signal)
+
+    return writer
+
 @block
 def initial_value_bench(initial_val, **kwargs):
 
@@ -107,9 +125,12 @@ def initial_value_bench(initial_val, **kwargs):
             else:
                 assert output_signal == update_val
 
-    @always(clk.posedge)
-    def output_writer():
-        print(output_signal)
+    if isinstance(initial_val, bool):
+        output_writer = bool_writer(output_signal, clk)
+
+    else:
+        output_writer = int_writer(output_signal, clk)
+
 
     return clkgen, output_driver, drive_and_check, output_writer
 
@@ -146,25 +167,31 @@ end process INITIAL_VALUE_BENCH_OUTPUT_WRITER;
 '''
     return list_writer
 
+@block
+def bool_list_writer(output_signal_list, clk):
+
+    signal_list_length = len(output_signal_list)
+
+    @always(clk.posedge)
+    def list_writer():
+        for i in range(signal_list_length):
+            print(int(output_signal_list[i]))
+
+    return list_writer
 
 @block
-def initial_value_list_bench(initial_vals, **kwargs):
+def initial_value_bool_list_bench(initial_vals, **kwargs):
     clk = Signal(bool(0))
 
     input_signal_list = [Signal(initial_val) for initial_val in initial_vals]
 
-    if len(initial_vals[0]) == 1:
-        output_signal_list = [
-            Signal(intbv(not initial_val, min=0, max=2)) for 
-            initial_val in initial_vals]
-        update_val = int(not initial_vals[0])
-    else:
-        output_signal_list = [
-            Signal(intbv(0, min=initial_val.min, max=initial_val.max)) for
-            initial_val in initial_vals]
-        update_val = 0
+    output_signal_list = [
+        Signal(not initial_val) for initial_val in initial_vals]
 
-    expected_output = [each_input._init for each_input in input_signal_list]
+    update_val = int(not initial_vals[0])
+
+    expected_output = [
+        bool(each_input._init) for each_input in input_signal_list]
 
     N = 10
     first = [True]
@@ -201,10 +228,81 @@ def initial_value_list_bench(initial_vals, **kwargs):
                 for i in range(signal_list_length):
                     assert output_signal_list[i] == update_val
 
-    output_writer = canonical_list_writer(output_signal_list, clk)
+    output_writer = bool_list_writer(output_signal_list, clk)
 
     return clkgen, output_driver, drive_and_check, output_writer
 
+@block
+def assign_output(input_signal, output_signal):
+    @always_comb
+    def assignment():
+        output_signal.next = input_signal
+
+    return assignment
+
+@block
+def initial_value_list_bench(initial_vals, **kwargs):
+    clk = Signal(bool(0))
+
+    input_signal_list = [Signal(initial_val) for initial_val in initial_vals]
+
+    if len(initial_vals[0]) == 1:
+
+        output_signal_list = [
+            Signal(intbv(not initial_val, min=0, max=2)) for
+            initial_val in initial_vals]
+        update_val = int(not initial_vals[0])
+    else:
+        output_signal_list = [
+            Signal(intbv(0, min=initial_val.min, max=initial_val.max)) for
+            initial_val in initial_vals]
+        update_val = 0
+
+    expected_output = [each_input._init for each_input in input_signal_list]
+
+    N = 10
+    first = [True]
+
+    signal_list_length = len(initial_vals)
+
+    @instance
+    def clkgen():
+
+        clk.next = 0
+        for n in range(N):
+            yield delay(10)
+            clk.next = not clk
+
+        raise StopSimulation()
+
+    # We assign each of the output drivers independently.
+    # This forces the output to be a wire (where appropriate) so we can
+    # check this type is handled properly too.
+    output_drivers = []
+    for input_signal, output_signal in zip(
+        input_signal_list, output_signal_list):
+
+        output_drivers.append(assign_output(input_signal, output_signal))
+
+    @always(clk.posedge)
+    def drive_and_check():
+
+        for i in range(signal_list_length):
+            input_signal_list[i].next = update_val
+
+        if __debug__:
+            if first[0]:
+                for i in range(signal_list_length):
+                    assert output_signal_list[i] == expected_output[i]
+                first[0] = False
+            else:
+                for i in range(signal_list_length):
+                    assert output_signal_list[i] == update_val
+
+    output_writer = canonical_list_writer(output_signal_list, clk)
+
+    return clkgen, output_drivers, drive_and_check, output_writer
+
 def runner(initial_val, tb=initial_value_bench, **kwargs):
     pre_toVerilog_initial_values = toVerilog.initial_values
     pre_toVHDL_initial_values = toVHDL.initial_values
@@ -242,6 +340,12 @@ def test_signed():
 
     runner(initial_val)
 
+def test_bool():
+    '''The correct initial value should be used for bool type signal.
+    '''
+    initial_val = bool(randrange(0, 2))
+    runner(initial_val)
+
 def test_modbv():
     '''The correct initial value should be used for modbv type signal.
     '''
@@ -344,12 +448,12 @@ def test_long_signals_list():
 def test_bool_signals_list():
     '''The correct initial value should be used for a boolean type signal lists
     '''
-    initial_vals = [intbv(0, min=0, max=2) for each in range(10)]
+    initial_vals = [False for each in range(10)]
 
-    runner(initial_vals, tb=initial_value_list_bench)
+    runner(initial_vals, tb=initial_value_bool_list_bench)
 
-    initial_vals = [intbv(0, min=0, max=2)] * 10
-    runner(initial_vals, tb=initial_value_list_bench)
+    initial_vals = [False] * 10
+    runner(initial_vals, tb=initial_value_bool_list_bench)
 
 
 def test_init_used():