mirror of
https://github.com/myhdl/myhdl.git
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function
This commit is contained in:
jand
parent
3c8272630a
commit
293300a625
@ -30,8 +30,9 @@ import operator
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import compiler
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from compiler import ast
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from sets import Set
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from types import GeneratorType, ClassType
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from types import GeneratorType, FunctionType, ClassType
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from cStringIO import StringIO
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import __builtin__
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import myhdl
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from myhdl import *
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@ -130,38 +131,31 @@ def _analyzeSigs(hierarchy):
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def LabelGenerator():
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i = 1
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while 1:
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yield "_MYHDL_LABEL_%s" % i
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yield "__MYHDL__%s" % i
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i += 1
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genLabel = LabelGenerator()
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def _analyzeGens(top, gennames):
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genLabel = LabelGenerator()
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genlist = []
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for g in top:
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f = g.gi_frame
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s = inspect.getsource(f)
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s = s.lstrip()
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gen = compiler.parse(s)
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gen.sourcefile = inspect.getsourcefile(f)
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gen.lineoffset = inspect.getsourcelines(f)[1]-1
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ast = compiler.parse(s)
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ast.sourcefile = inspect.getsourcefile(f)
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ast.lineoffset = inspect.getsourcelines(f)[1]-1
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symdict = f.f_globals.copy()
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symdict.update(f.f_locals)
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# print f.f_locals
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sigdict = {}
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for n, v in symdict.items():
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if isinstance(v, Signal):
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sigdict[n] = v
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gen.sigdict = sigdict
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gen.symdict = symdict
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if gennames.has_key(id(g)):
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gen.name = gennames[id(g)]
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else:
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gen.name = genLabel.next()
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v = _AnalyzeGenVisitor(sigdict, symdict, gen.sourcefile, gen.lineoffset)
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compiler.walk(gen, v)
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gen.vardict = v.vardict
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gen.kind = v.kind
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genlist.append(gen)
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ast.symdict = symdict
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ast.name = gennames.get(id(g), genLabel.next() + "_BLOCK")
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v = _AnalyzeBlockVisitor(symdict, ast.sourcefile, ast.lineoffset)
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compiler.walk(ast, v)
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ast.sigdict = v.sigdict
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ast.vardict = v.vardict
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ast.kind = v.kind
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genlist.append(ast)
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return genlist
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@ -247,8 +241,6 @@ class _NotSupportedVisitor(_ToVerilogMixin):
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def visitList(self, node, *args):
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self.raiseError(node, _error.NotSupported, "list")
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def visitReturn(self, node, *args):
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self.raiseError(node, _error.NotSupported, "return statement")
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def visitTryExcept(self, node, *args):
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self.raiseError(node, _error.NotSupported, "try-except statement")
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@ -262,22 +254,25 @@ def getObj(node):
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return node.obj
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return None
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def getNrBits(obj):
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if hasattr(obj, '_nrbits'):
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return obj._nrbits
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return None
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INPUT, OUTPUT, INOUT = range(3)
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NORMAL, DECLARATION = range(2)
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ALWAYS, INITIAL = range(2)
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class _AnalyzeGenVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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def __init__(self, sigdict, symdict, sourcefile, lineoffset):
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def __init__(self, symdict, sourcefile, lineoffset):
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self.sourcefile = sourcefile
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self.lineoffset = lineoffset
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self.inputs = Set()
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self.outputs = Set()
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self.toplevel = 1
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self.sigdict = sigdict
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self.symdict = symdict
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self.vardict = {}
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self.used = Set()
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def getObj(self, node):
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if hasattr(node, 'obj'):
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@ -315,7 +310,12 @@ class _AnalyzeGenVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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def visitAssName(self, node, *args):
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n = node.name
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self.require(node, n not in self.symdict, "Illegal redeclaration: %s" % n)
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# XXX ?
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if n in self.vardict:
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return
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if n in self.used:
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self.require(node, n not in self.symdict,
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"Previously used external symbol cannot be locally redeclared: %s" % n)
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def visitAugAssign(self, node, access=INPUT, *args):
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self.visit(node.node, INOUT)
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@ -324,10 +324,34 @@ class _AnalyzeGenVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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def visitCallFunc(self, node, *args):
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for child in node.getChildNodes():
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self.visit(child, *args)
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f = self.getObj(node.node)
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func = self.getObj(node.node)
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# print f
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if type(f) is type and issubclass(f, intbv):
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# print node.args
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if type(func) is type and issubclass(func, intbv):
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node.obj = intbv()
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elif func in myhdl.__dict__.values():
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pass
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elif func in __builtin__.__dict__.values():
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pass
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elif type(func) is FunctionType:
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s = inspect.getsource(func)
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s = s.lstrip()
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ast = compiler.parse(s)
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print ast
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ast.name = genLabel.next() + "_" + func.__name__
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ast.sourcefile = inspect.getsourcefile(func)
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ast.lineoffset = inspect.getsourcelines(func)[1]-1
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ast.symdict = func.func_globals.copy()
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v = _AnalyzeFuncVisitor(ast.symdict, ast.sourcefile, ast.lineoffset, \
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self.inputs, self.outputs, node.args)
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compiler.walk(ast, v)
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ast.sigdict = v.sigdict
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ast.vardict = v.vardict
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ast.argnames = v.argnames
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ast.returnObj = v.returnObj
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# print ast.argnames
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ast.kind = v.kind
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node.ast = ast
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def visitCompare(self, node, *args):
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node.obj = bool()
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@ -348,23 +372,9 @@ class _AnalyzeGenVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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self.visit(node.list)
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self.visit(node.body, *args)
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self.require(node, node.else_ is None, "for-else not supported")
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def visitFunction(self, node, *args):
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if not self.toplevel:
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self.raiseError(node, _error.NotSupported, "embedded function definition")
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self.toplevel = 0
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print node.code
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self.visit(node.code)
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self.kind = ALWAYS
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for n in node.code.nodes[:-1]:
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if not self.getKind(n) == DECLARATION:
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self.kind = INITIAL
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break
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if self.kind == ALWAYS:
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w = node.code.nodes[-1]
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if not self.getKind(w) == ALWAYS:
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self.kind = INITIAL
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def visitFunction(self, node, *args):
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raise AssertionError
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def visitGetattr(self, node, *args):
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self.visit(node.expr, *args)
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@ -375,22 +385,9 @@ class _AnalyzeGenVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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assert hasattr(obj, node.attrname)
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node.obj = getattr(obj, node.attrname)
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def visitModule(self, node, *args):
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print node
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#assert len(node.node.nodes) == 1
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#assert isinstance(node.node.nodes[0], ast.Function)
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self.visit(node.node)
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for n in self.outputs:
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s = self.sigdict[n]
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if s._driven:
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self.raiseError(node, _error._SigMultipleDriven, n)
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s._driven = True
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for n in self.inputs:
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s = self.sigdict[n]
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s._read = True
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def visitName(self, node, access=INPUT, *args):
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n = node.name
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self.used.add(n)
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if n in self.sigdict:
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if access == INPUT:
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self.inputs.add(n)
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@ -403,8 +400,14 @@ class _AnalyzeGenVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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node.obj = self.vardict[n]
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elif n in self.symdict:
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node.obj = self.symdict[n]
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elif n in __builtins__:
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else:
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#print "HERE"
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#print __builtins__[n]
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node.obj = __builtins__[n]
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def visitReturn(self, node, *args):
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self.visit(node.value)
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def visitSlice(self, node, access=INPUT, kind=NORMAL, *args):
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self.visit(node.expr, access)
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@ -439,14 +442,114 @@ class _AnalyzeGenVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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node.kind = ALWAYS
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self.require(node, node.else_ is None, "while-else not supported")
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class _AnalyzeBlockVisitor(_AnalyzeVisitor):
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def __init__(self, symdict, sourcefile, lineoffset):
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_AnalyzeVisitor.__init__(self, symdict, sourcefile, lineoffset)
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self.sigdict = sigdict = {}
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for n, v in symdict.items():
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if isinstance(v, Signal):
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sigdict[n] = v
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self.inputs = Set()
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self.outputs = Set()
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def visitFunction(self, node, *args):
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if not self.toplevel:
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self.raiseError(node, _error.NotSupported, "embedded function definition")
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self.toplevel = 0
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print node.code
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self.visit(node.code)
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self.kind = ALWAYS
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for n in node.code.nodes[:-1]:
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if not self.getKind(n) == DECLARATION:
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self.kind = INITIAL
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break
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if self.kind == ALWAYS:
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w = node.code.nodes[-1]
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if not self.getKind(w) == ALWAYS:
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self.kind = INITIAL
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def visitModule(self, node, *args):
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#assert len(node.node.nodes) == 1
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#assert isinstance(node.node.nodes[0], ast.Function)
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self.visit(node.node)
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for n in self.outputs:
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s = self.sigdict[n]
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if s._driven:
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self.raiseError(node, _error._SigMultipleDriven, n)
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s._driven = True
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for n in self.inputs:
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s = self.sigdict[n]
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s._read = True
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def visitReturn(self, node, *args):
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self.raiseError(node, _error.NotSupported, "return statement")
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class _AnalyzeFuncVisitor(_AnalyzeVisitor):
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def __init__(self, symdict, sourcefile, lineoffset, \
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inputs, outputs, args):
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_AnalyzeVisitor.__init__(self, symdict, sourcefile, lineoffset)
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self.sigdict = sigdict = {}
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self.inputs = inputs
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self.outputs = outputs
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self.args = args
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self.argnames = []
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self.kind = None
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self.hasReturn = False
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def visitFunction(self, node, *args):
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if not self.toplevel:
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self.raiseError(node, _error.NotSupported, "embedded function definition")
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self.toplevel = 0
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argnames = node.argnames
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for i, arg in enumerate(self.args):
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if isinstance(arg, ast.Keyword):
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n = arg.name
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self.symdict[n] = getObj(arg.expr)
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else: # Name
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n = argnames[i]
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self.symdict[n] = getObj(arg)
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self.argnames.append(n)
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for n, v in self.symdict.items():
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if isinstance(v, Signal):
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self.sigdict[n] = v
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self.visit(node.code)
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def visitReturn(self, node, *args):
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self.visit(node.value)
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if isinstance(node.value, ast.Const) and node.value.value is None:
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obj = None
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elif isinstance(node.value, ast.Name) and node.value.name is None:
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obj = None
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elif node.value.obj is not None:
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obj = node.value.obj
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else:
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self.raiseError(node, "Can't derive return type")
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if self.hasReturn:
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returnObj = self.returnObj
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if getNrBits(obj) != getNrBits(returnObj):
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self.raiseError(node, "Returned nr of bits is different from before")
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if isinstance(obj, type(returnObj)):
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pass
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elif isinstance(returnObj, type(obj)):
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self.returnObj = type(obj)
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else:
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self.raiseError(node, "Incompatible return type")
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else:
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self.returnObj = obj
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self.hasReturn = True
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def _analyzeTopFunc(func, *args, **kwargs):
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s = inspect.getsource(func)
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s = s.lstrip()
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funcast = compiler.parse(s)
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ast = compiler.parse(s)
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v = _AnalyzeTopFuncVisitor(*args, **kwargs)
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compiler.walk(funcast, v)
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compiler.walk(ast, v)
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return v
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@ -570,29 +673,34 @@ def _getRangeString(s):
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def _convertGens(genlist, vfile):
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for gen in genlist:
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if gen.kind == ALWAYS:
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blockBuf = StringIO()
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funcBuf = StringIO()
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for ast in genlist:
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if ast.kind == ALWAYS:
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Visitor = _ConvertAlwaysVisitor
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else:
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Visitor = _ConvertInitialVisitor
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v = Visitor(vfile, gen.sigdict, gen.symdict, gen.vardict,
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gen.name, gen.sourcefile, gen.lineoffset )
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compiler.walk(gen, v)
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v = Visitor(ast, blockBuf, funcBuf)
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compiler.walk(ast, v)
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#print "FUNC"
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#print funcBuf.getvalue()
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#print "BLOCK"
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#print blockBuf.getvalue()
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vfile.write(funcBuf.getvalue()); funcBuf.close()
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vfile.write(blockBuf.getvalue()); blockBuf.close()
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class _ConvertGenVisitor(_ToVerilogMixin):
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class _ConvertVisitor(_ToVerilogMixin):
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def __init__(self, f, sigdict, symdict, vardict, name, sourcefile, lineoffset):
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self.buf = self.fileBuf = f
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self.name = name
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self.sourcefile = sourcefile
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self.lineoffset = lineoffset
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self.declBuf = StringIO()
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self.codeBuf = StringIO()
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self.sigdict = sigdict
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self.symdict = symdict
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self.vardict = vardict
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print vardict
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def __init__(self, ast, blockBuf, funcBuf=None):
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self.buf = blockBuf
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self.funcBuf = funcBuf
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self.name = ast.name
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self.sourcefile = ast.sourcefile
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self.lineoffset = ast.lineoffset
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self.sigdict = ast.sigdict
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self.symdict = ast.symdict
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self.vardict = ast.vardict
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self.ind = ''
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self.inYield = False
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self.isSigAss = False
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@ -672,9 +780,30 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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self.write(node.name)
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def visitAugAssign(self, node):
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# XXX
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pass
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opmap = {"+=" : "+",
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"-=" : "-",
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"*=" : "*",
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"//=" : "/",
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"%=" : "%",
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"**=" : "**",
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"|=" : "|",
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">>=" : ">>",
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"<<=" : "<<",
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"&=" : "&",
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"^=" : "^"
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}
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if node.op not in opmap:
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self.raiseError(node, _error.NotSupported,
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"augmented assignment %s" % op)
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op = opmap[node.op]
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self.writeline()
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self.visit(node.node)
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self.write(" = ")
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self.visit(node.node)
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self.write(" %s " % op)
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self.visit(node.expr)
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self.write(";")
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def visitBitand(self, node):
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self.multiOp(node, '&')
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@ -704,6 +833,8 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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self.write(": ")
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elif f is concat:
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opening, closing = '{', '}'
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elif hasattr(node, 'ast'):
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self.write(node.ast.name)
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else:
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self.write(f.__name__)
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self.write(opening)
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@ -713,6 +844,11 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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self.write(", ")
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self.visit(arg)
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self.write(closing)
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if hasattr(node, 'ast'):
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Visitor = _ConvertFunctionVisitor
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v = Visitor(node.ast, self.funcBuf)
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compiler.walk(node.ast, v)
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def visitCompare(self, node):
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self.write("(")
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@ -731,7 +867,6 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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def visitFor(self, node):
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var = node.assign.name
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self.buf = self.codeBuf
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cf = node.list
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self.require(node, isinstance(cf, ast.CallFunc), "Expected (down)range call")
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f = getObj(cf.node)
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@ -826,8 +961,7 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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self.write(")")
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def visitKeyword(self, node):
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# XXX
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pass
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self.visit(node.expr)
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def visitLeftShift(self, node):
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self.binaryOp(node, '<<')
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@ -843,16 +977,19 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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self.binaryOp(node, '*')
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def visitName(self, node):
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if node.name in self.symdict:
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obj = self.symdict[node.name]
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n = node.name
|
||||
if n in self.vardict:
|
||||
self.write(n)
|
||||
elif node.name in self.symdict:
|
||||
obj = self.symdict[n]
|
||||
if isinstance(obj, int):
|
||||
self.write(str(obj))
|
||||
elif type(obj) is Signal:
|
||||
self.write(obj._name)
|
||||
else:
|
||||
self.write(node.name)
|
||||
self.write(n)
|
||||
else:
|
||||
self.write(node.name)
|
||||
raise AssertionError
|
||||
|
||||
def visitNot(self, node):
|
||||
self.write("(!")
|
||||
@ -892,6 +1029,12 @@ class _ConvertGenVisitor(_ToVerilogMixin):
|
||||
def visitSlice(self, node):
|
||||
# print dir(node)
|
||||
# print node.obj
|
||||
if isinstance(node.expr, ast.CallFunc) and \
|
||||
node.expr.node.obj is intbv:
|
||||
c = self.getVal(node)
|
||||
self.write("%s'h" % c._len)
|
||||
self.write("%x" % c._val)
|
||||
return
|
||||
self.visit(node.expr)
|
||||
self.write("[")
|
||||
if node.lower is None:
|
||||
@ -948,10 +1091,10 @@ class _ConvertGenVisitor(_ToVerilogMixin):
|
||||
self.inYield = False
|
||||
|
||||
|
||||
class _ConvertAlwaysVisitor(_ConvertGenVisitor):
|
||||
class _ConvertAlwaysVisitor(_ConvertVisitor):
|
||||
|
||||
def __init__(self, *args):
|
||||
_ConvertGenVisitor.__init__(self, *args)
|
||||
_ConvertVisitor.__init__(self, *args)
|
||||
|
||||
def visitFunction(self, node):
|
||||
w = node.code.nodes[-1]
|
||||
@ -964,36 +1107,94 @@ class _ConvertAlwaysVisitor(_ConvertGenVisitor):
|
||||
self.write(") begin: %s" % self.name)
|
||||
self.indent()
|
||||
self.writeDeclarations()
|
||||
self.buf = self.codeBuf
|
||||
for s in w.body.nodes[1:]:
|
||||
self.visit(s)
|
||||
self.buf = self.fileBuf
|
||||
self.write(self.codeBuf.getvalue())
|
||||
self.dedent()
|
||||
self.writeline()
|
||||
self.write("end")
|
||||
self.writeline()
|
||||
self.writeline()
|
||||
|
||||
class _ConvertInitialVisitor(_ConvertGenVisitor):
|
||||
class _ConvertInitialVisitor(_ConvertVisitor):
|
||||
|
||||
def __init__(self, *args):
|
||||
_ConvertGenVisitor.__init__(self, *args)
|
||||
_ConvertVisitor.__init__(self, *args)
|
||||
|
||||
def visitFunction(self, node):
|
||||
self.inYield = True
|
||||
self.write("initial begin: %s" % self.name)
|
||||
self.indent()
|
||||
self.writeDeclarations()
|
||||
self.buf = self.codeBuf
|
||||
self.visit(node.code)
|
||||
self.buf = self.fileBuf
|
||||
self.write(self.codeBuf.getvalue())
|
||||
self.dedent()
|
||||
self.writeline()
|
||||
self.write("end")
|
||||
self.writeline()
|
||||
self.writeline()
|
||||
|
||||
|
||||
class _ConvertFunctionVisitor(_ConvertVisitor):
|
||||
|
||||
def __init__(self, ast, blockBuf, funcBuf=None):
|
||||
_ConvertVisitor.__init__(self, ast, blockBuf, funcBuf)
|
||||
self.argnames = ast.argnames
|
||||
self.returnObj = ast.returnObj
|
||||
|
||||
def writeOutputDeclaration(self):
|
||||
obj = self.returnObj
|
||||
if type(obj) is bool:
|
||||
pass
|
||||
elif isinstance(obj, int):
|
||||
self.write("integer")
|
||||
elif isinstance(obj, intbv):
|
||||
self.write("[%s-1:0]" % obj._len)
|
||||
elif hasattr(obj, '_nrbits'):
|
||||
self.write("[%s-1:0]" % obj._nrbits)
|
||||
else:
|
||||
raise AssertionError("unexpected type")
|
||||
|
||||
def writeInputDeclarations(self):
|
||||
for name in self.argnames:
|
||||
obj = self.symdict[name]
|
||||
self.writeline()
|
||||
if type(obj) is bool:
|
||||
self.write("input %s;" % name)
|
||||
elif isinstance(obj, int):
|
||||
self.write("integer %s;" % name)
|
||||
elif isinstance(obj, intbv):
|
||||
self.write("input [%s-1:0] %s;" % (obj._len, name))
|
||||
elif hasattr(obj, '_nrbits'):
|
||||
self.write("input [%s-1:0] %s;" % (obj._nrbits, name))
|
||||
else:
|
||||
raise AssertionError("unexpected type")
|
||||
|
||||
def visitFunction(self, node):
|
||||
self.write("function ")
|
||||
self.writeOutputDeclaration()
|
||||
self.write(" %s;" % self.name)
|
||||
self.indent()
|
||||
self.writeInputDeclarations()
|
||||
self.writeDeclarations()
|
||||
self.writeline()
|
||||
self.write("begin: __MYHDL__")
|
||||
self.visit(node.code)
|
||||
self.dedent()
|
||||
self.writeline()
|
||||
self.write("end")
|
||||
self.writeline()
|
||||
self.write("endfunction")
|
||||
self.writeline()
|
||||
self.writeline()
|
||||
|
||||
def visitReturn(self, node):
|
||||
self.writeline()
|
||||
self.write("%s = " % self.name)
|
||||
self.visit(node.value)
|
||||
self.write(";")
|
||||
self.writeline()
|
||||
self.write("disable __MYHDL__;")
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -144,9 +144,11 @@ class _UnparseVisitor(object):
|
||||
def visitSlice(self, node):
|
||||
self.visit(node.expr)
|
||||
self.write('[')
|
||||
self.visit(node.lower)
|
||||
if node.lower is not None:
|
||||
self.visit(node.lower)
|
||||
self.write(':')
|
||||
self.visit(node.upper)
|
||||
if node.upper is not None:
|
||||
self.visit(node.upper)
|
||||
self.write(']')
|
||||
|
||||
def visitSub(self, node):
|
||||
|
||||
@ -7,9 +7,10 @@ from myhdl import *
|
||||
|
||||
COSET = 0x55
|
||||
|
||||
def calculateHec(header):
|
||||
""" Return hec for an ATM header, represented as an intbv.
|
||||
def calculateHecRef(header):
|
||||
""" Return hec for an ATM header.
|
||||
|
||||
Reference version.
|
||||
The hec polynomial is 1 + x + x**2 + x**8.
|
||||
"""
|
||||
hec = intbv(0)
|
||||
@ -21,8 +22,28 @@ def calculateHec(header):
|
||||
)
|
||||
return hec ^ COSET
|
||||
|
||||
def calculateHecSynth(header):
|
||||
""" Return hec for an ATM header.
|
||||
|
||||
Synthesizable version.
|
||||
The hec polynomial is 1 + x + x**2 + x**8.
|
||||
"""
|
||||
h = intbv(0)[8:]
|
||||
for i in downrange(len(header)):
|
||||
bit = header[i]
|
||||
h[:] = concat(h[7:2],
|
||||
bit ^ h[1] ^ h[7],
|
||||
bit ^ h[0] ^ h[7],
|
||||
bit ^ h[7]
|
||||
)
|
||||
h ^= COSET
|
||||
return h
|
||||
|
||||
def HecCalculator(hec, header):
|
||||
def HecCalculatorPlain(hec, header):
|
||||
""" Hec calculation module.
|
||||
|
||||
Plain version.
|
||||
"""
|
||||
h = intbv(0)[8:]
|
||||
while 1:
|
||||
yield header
|
||||
@ -35,6 +56,18 @@ def HecCalculator(hec, header):
|
||||
bit ^ h[7]
|
||||
)
|
||||
hec.next = h ^ COSET
|
||||
|
||||
def HecCalculatorFunc(hec, header):
|
||||
""" Hec calculation module.
|
||||
|
||||
Version with function call.
|
||||
"""
|
||||
h = intbv(0)[8:]
|
||||
while 1:
|
||||
yield header
|
||||
hec.next = calculateHecSynth(header=header)
|
||||
|
||||
|
||||
|
||||
objfile = "heccalc.o"
|
||||
analyze_cmd = "iverilog -o %s heccalc_inst.v tb_heccalc_inst.v" % objfile
|
||||
@ -46,13 +79,6 @@ def HecCalculator_v(hec, header):
|
||||
os.system(analyze_cmd)
|
||||
return Cosimulation(simulate_cmd, **locals())
|
||||
|
||||
hec = Signal(intbv(0)[8:])
|
||||
hec_v = Signal(intbv(0)[8:])
|
||||
header = Signal(intbv(-1)[32:])
|
||||
|
||||
heccalc_inst = toVerilog(HecCalculator, hec, header)
|
||||
# heccalc_inst = HecCalculator(hec, header)
|
||||
heccalc_v_inst = HecCalculator_v(hec_v, header)
|
||||
|
||||
|
||||
headers = [ 0x00000000L,
|
||||
@ -64,17 +90,36 @@ headers.extend([randrange(2**32-1) for i in range(10)])
|
||||
|
||||
class TestHec(unittest.TestCase):
|
||||
|
||||
def stimulus(self):
|
||||
for h in headers:
|
||||
header.next = h
|
||||
yield delay(10)
|
||||
print "hec: %s hec_v: %s" % (hex(hec), hex(hec_v))
|
||||
self.assertEqual(hec, hec_v)
|
||||
def bench(self, HecCalculator):
|
||||
|
||||
hec = Signal(intbv(0)[8:])
|
||||
hec_v = Signal(intbv(0)[8:])
|
||||
header = Signal(intbv(-1)[32:])
|
||||
|
||||
def test(self):
|
||||
sim = self.stimulus(), heccalc_inst, heccalc_v_inst
|
||||
heccalc_inst = toVerilog(HecCalculator, hec, header)
|
||||
# heccalc_inst = HecCalculator(hec, header)
|
||||
heccalc_v_inst = HecCalculator_v(hec_v, header)
|
||||
|
||||
def stimulus():
|
||||
for h in headers:
|
||||
header.next = h
|
||||
yield delay(10)
|
||||
hec_ref = calculateHecRef(header)
|
||||
# print "hec: %s hec_v: %s" % (hex(hec), hex(hec_v))
|
||||
self.assertEqual(hec, hec_ref)
|
||||
self.assertEqual(hec, hec_v)
|
||||
|
||||
return stimulus(), heccalc_inst, heccalc_v_inst
|
||||
|
||||
def testPlain(self):
|
||||
sim = self.bench(HecCalculatorPlain)
|
||||
Simulation(sim).run()
|
||||
|
||||
def testFunc(self):
|
||||
sim = self.bench(HecCalculatorFunc)
|
||||
Simulation(sim).run()
|
||||
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
unittest.main()
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user