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https://github.com/myhdl/myhdl.git
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tasks
This commit is contained in:
jand
parent
294d705a2f
commit
2acf4df28d
@ -41,7 +41,6 @@ from myhdl._extractHierarchy import _HierExtr, _findInstanceName
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from myhdl._util import _flatten
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from myhdl._unparse import _unparse
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_converting = 0
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_profileFunc = None
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@ -55,13 +54,11 @@ _error.UndefinedBitWidth = "Signal has undefined bit width"
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_error.UndrivenSignal = "Signal is not driven"
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_error.Requirement = "Requirement violation"
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def _checkArgs(arglist):
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for arg in arglist:
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if not type(arg) is GeneratorType:
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raise ArgumentError
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def toVerilog(func, *args, **kwargs):
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global _converting
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if _converting:
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@ -244,7 +241,7 @@ def getNrBits(obj):
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return None
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INPUT, OUTPUT, INOUT = range(3)
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INPUT, OUTPUT, INOUT, UNKNOWN = range(4)
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NORMAL, DECLARATION = range(2)
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ALWAYS, INITIAL = range(2)
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@ -256,6 +253,8 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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self.toplevel = 1
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self.symdict = symdict
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self.vardict = {}
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self.inputs = Set()
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self.outputs = Set()
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self.used = Set()
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self.labelStack = []
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@ -318,11 +317,11 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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self.labelStack[-2].isActive = True
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def visitCallFunc(self, node, *args):
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for child in node.getChildNodes():
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self.visit(child, *args)
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self.visit(node.node)
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for arg in node.args:
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self.visit(arg, UNKNOWN)
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argsAreInputs = True
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func = self.getObj(node.node)
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# print f
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# print node.args
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if type(func) is type and issubclass(func, intbv):
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node.obj = intbv()
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elif func is len:
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@ -332,6 +331,7 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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elif func in __builtin__.__dict__.values():
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pass
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elif type(func) is FunctionType:
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argsAreInputs = False
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s = inspect.getsource(func)
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s = s.lstrip()
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ast = compiler.parse(s)
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@ -340,16 +340,31 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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ast.sourcefile = inspect.getsourcefile(func)
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ast.lineoffset = inspect.getsourcelines(func)[1]-1
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ast.symdict = func.func_globals.copy()
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v = _AnalyzeFuncVisitor(ast.symdict, ast.sourcefile, ast.lineoffset, \
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self.inputs, self.outputs, node.args)
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v = _AnalyzeFuncVisitor(ast.symdict, ast.sourcefile, ast.lineoffset, node.args)
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compiler.walk(ast, v)
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ast.sigdict = v.sigdict
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ast.vardict = v.vardict
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ast.argnames = v.argnames
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ast.inputs = v.inputs
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ast.outputs = v.outputs
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ast.returnObj = v.returnObj
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# print ast.argnames
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ast.kind = v.kind
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node.ast = ast
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print "FUNCTION inputs %s outputs %s" % (ast.inputs, ast.outputs)
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for i, arg in enumerate(node.args):
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if isinstance(arg, compiler.ast.Keyword):
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n = arg.name
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else: # Name
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n = ast.argnames[i]
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if n in ast.outputs:
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print "ARG"
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print arg
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self.visit(arg, OUTPUT)
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if n in ast.inputs:
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self.visit(arg, INPUT)
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if argsAreInputs:
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for arg in node.args:
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self.visit(arg, INPUT)
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def visitCompare(self, node, *args):
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node.obj = bool()
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@ -399,6 +414,8 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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self.inputs.add(n)
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elif access == OUTPUT:
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self.outputs.add(n)
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elif access == UNKNOWN:
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pass
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else:
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raise AssertionError
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node.obj = None
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@ -407,8 +424,6 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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elif n in self.symdict:
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node.obj = self.symdict[n]
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else:
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#print "HERE"
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#print __builtins__[n]
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node.obj = __builtins__[n]
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def visitReturn(self, node, *args):
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@ -463,8 +478,6 @@ class _AnalyzeBlockVisitor(_AnalyzeVisitor):
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for n, v in symdict.items():
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if isinstance(v, Signal):
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sigdict[n] = v
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self.inputs = Set()
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self.outputs = Set()
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def visitFunction(self, node, *args):
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if not self.toplevel:
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@ -483,8 +496,6 @@ class _AnalyzeBlockVisitor(_AnalyzeVisitor):
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self.kind = INITIAL
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def visitModule(self, node, *args):
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#assert len(node.node.nodes) == 1
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#assert isinstance(node.node.nodes[0], ast.Function)
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self.visit(node.node)
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for n in self.outputs:
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s = self.sigdict[n]
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@ -501,16 +512,14 @@ class _AnalyzeBlockVisitor(_AnalyzeVisitor):
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class _AnalyzeFuncVisitor(_AnalyzeVisitor):
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def __init__(self, symdict, sourcefile, lineoffset, \
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inputs, outputs, args):
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def __init__(self, symdict, sourcefile, lineoffset, args):
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_AnalyzeVisitor.__init__(self, symdict, sourcefile, lineoffset)
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self.sigdict = sigdict = {}
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self.inputs = inputs
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self.outputs = outputs
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self.args = args
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self.argnames = []
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self.kind = None
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self.hasReturn = False
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self.returnObj = None
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def visitFunction(self, node, *args):
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if not self.toplevel:
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@ -526,10 +535,11 @@ class _AnalyzeFuncVisitor(_AnalyzeVisitor):
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self.symdict[n] = getObj(arg)
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self.argnames.append(n)
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for n, v in self.symdict.items():
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if isinstance(v, Signal):
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if isinstance(v, (Signal, intbv)):
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self.sigdict[n] = v
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self.visit(node.code)
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def visitReturn(self, node, *args):
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self.visit(node.value)
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if isinstance(node.value, ast.Const) and node.value.value is None:
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@ -774,7 +784,6 @@ class _ConvertVisitor(_ToVerilogMixin):
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pass
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def visitAssign(self, node):
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self.writeline()
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assert len(node.nodes) == 1
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self.visit(node.nodes[0])
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if self.isSigAss:
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@ -805,7 +814,6 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.raiseError(node, _error.NotSupported,
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"augmented assignment %s" % node.op)
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op = opmap[node.op]
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self.writeline()
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self.visit(node.node)
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self.write(" = ")
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self.visit(node.node)
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@ -858,7 +866,10 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.visit(arg)
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self.write(closing)
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if hasattr(node, 'ast'):
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Visitor = _ConvertFunctionVisitor
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if node.ast.outputs:
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Visitor = _ConvertTaskVisitor
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else:
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Visitor = _ConvertFunctionVisitor
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v = Visitor(node.ast, self.funcBuf)
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compiler.walk(node.ast, v)
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@ -878,6 +889,13 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.writeline()
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self.write("disable %s;" % self.labelStack[-1])
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def visitDiscard(self, node):
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expr = node.expr
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self.visit(expr)
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# ugly hack to detect an orphan "task" call
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if isinstance(expr, ast.CallFunc) and hasattr(expr, 'ast'):
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self.write(';')
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def visitFloorDiv(self, node):
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self.binaryOp(node, '/')
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@ -912,9 +930,8 @@ class _ConvertVisitor(_ToVerilogMixin):
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else:
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start, stop, step = args
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if node.breakLabel.isActive:
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self.writeline()
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self.write("begin: %s" % node.breakLabel)
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self.writeline()
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self.writeline()
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self.write("for (%s=" % var)
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if start is None:
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self.write("0")
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@ -961,9 +978,14 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.write("%d'b%s" % (obj._nrbits, e._val))
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def visitIf(self, node):
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ifstring = "if ("
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first = True
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for test, suite in node.tests:
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self.writeline()
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if first:
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ifstring = "if ("
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first = False
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else:
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ifstring = "else if ("
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self.writeline()
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self.write(ifstring)
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self.visit(test)
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self.write(") begin")
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@ -972,7 +994,6 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.dedent()
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self.writeline()
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self.write("end")
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ifstring = "else if ("
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if node.else_:
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self.writeline()
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self.write("else begin")
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@ -1043,12 +1064,14 @@ class _ConvertVisitor(_ToVerilogMixin):
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pass
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def visitRaise(self, node):
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self.writeline()
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self.write('$display("Verilog: ')
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self.visit(node.expr1)
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self.write('");')
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self.writeline()
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self.write("$finish;")
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def visitReturn(self, node):
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self.write("disable %s;" % self.name)
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def visitRightShift(self, node):
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self.binaryOp(node, '>>')
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@ -1074,6 +1097,14 @@ class _ConvertVisitor(_ToVerilogMixin):
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else:
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self.visit(node.upper)
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self.write("]")
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def visitStmt(self, node):
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for stmt in node.nodes:
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self.writeline()
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self.visit(stmt)
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# ugly hack to detect an orphan "task" call
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if isinstance(stmt, ast.CallFunc) and hasattr(stmt, 'ast'):
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self.write(';')
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def visitSub(self, node):
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self.binaryOp(node, "-")
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@ -1150,8 +1181,10 @@ class _ConvertAlwaysVisitor(_ConvertVisitor):
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self.write(") begin: %s" % self.name)
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self.indent()
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self.writeDeclarations()
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for s in w.body.nodes[1:]:
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self.visit(s)
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assert isinstance(w.body, ast.Stmt)
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for stmt in w.body.nodes[1:]:
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self.writeline()
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self.visit(stmt)
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self.dedent()
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self.writeline()
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self.write("end")
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@ -1180,6 +1213,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
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_ConvertVisitor.__init__(self, ast, funcBuf)
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self.argnames = ast.argnames
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self.returnObj = ast.returnObj
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self.returnLabel = Label("RETURN")
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def writeOutputDeclaration(self):
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obj = self.returnObj
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@ -1213,21 +1247,63 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
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self.writeInputDeclarations()
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self.writeDeclarations()
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self.writeline()
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self.write("begin: __MYHDL__")
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self.write("begin: %s" % self.returnLabel)
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self.visit(node.code)
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self.dedent()
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self.writeline()
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self.write("end")
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self.dedent()
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self.writeline()
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self.write("endfunction")
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self.writeline(2)
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def visitReturn(self, node):
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self.writeline()
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self.write("%s = " % self.name)
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self.visit(node.value)
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self.write(";")
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self.writeline()
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self.write("disable __MYHDL__;")
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self.write("disable %s;" % self.returnLabel)
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class _ConvertTaskVisitor(_ConvertVisitor):
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def __init__(self, ast, funcBuf):
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_ConvertVisitor.__init__(self, ast, funcBuf)
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self.argnames = ast.argnames
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self.inputs = ast.inputs
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self.outputs = ast.outputs
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def writeInterfaceDeclarations(self):
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for name in self.argnames:
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obj = self.symdict[name]
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output = name in self.outputs
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input = name in self.inputs
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inout = input and output
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dir = inout and "inout" or output and "output" or input and "input"
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self.writeline()
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if type(obj) is bool:
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self.write("%s %s;" % (dir, name))
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elif isinstance(obj, int):
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self.write("integer %s;" % name)
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elif hasattr(obj, '_nrbits'):
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self.write("%s [%s-1:0] %s;" % (dir, obj._nrbits, name))
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else:
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raise AssertionError("unexpected type")
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def visitFunction(self, node):
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self.write("task %s;" % self.name)
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self.indent()
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self.writeInterfaceDeclarations()
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self.writeDeclarations()
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self.writeline()
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self.write("begin")
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self.visit(node.code)
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self.writeline()
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self.write("end")
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self.dedent()
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self.writeline()
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self.write("endtask")
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self.writeline(2)
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@ -22,10 +22,10 @@ def calculateHecRef(header):
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)
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return hec ^ COSET
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def calculateHecSynth(header):
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def calculateHecFunc(header):
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""" Return hec for an ATM header.
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Synthesizable version.
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Translatable version.
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The hec polynomial is 1 + x + x**2 + x**8.
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"""
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h = intbv(0)[8:]
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@ -39,6 +39,23 @@ def calculateHecSynth(header):
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h ^= COSET
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return h
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def calculateHecTask(hec, header):
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""" Calculate hec for an ATM header.
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Translatable version.
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The hec polynomial is 1 + x + x**2 + x**8.
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"""
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h = intbv(0)[8:]
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for i in downrange(len(header)):
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bit = header[i]
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h[:] = concat(h[7:2],
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bit ^ h[1] ^ h[7],
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bit ^ h[0] ^ h[7],
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bit ^ h[7]
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)
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h ^= COSET
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hec[:] = h
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def HecCalculatorPlain(hec, header):
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""" Hec calculation module.
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@ -65,7 +82,18 @@ def HecCalculatorFunc(hec, header):
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h = intbv(0)[8:]
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while 1:
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yield header
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hec.next = calculateHecSynth(header=header)
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hec.next = calculateHecFunc(header=header)
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def HecCalculatorTask(hec, header):
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""" Hec calculation module.
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Version with task call.
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"""
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h = intbv(0)[8:]
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while 1:
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yield header
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calculateHecTask(h, header)
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hec.next = h
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@ -105,19 +133,24 @@ class TestHec(unittest.TestCase):
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header.next = h
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yield delay(10)
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hec_ref = calculateHecRef(header)
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# print "hec: %s hec_v: %s" % (hex(hec), hex(hec_v))
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print "hec: %s hec_v: %s" % (hex(hec), hex(hec_v))
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self.assertEqual(hec, hec_ref)
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self.assertEqual(hec, hec_v)
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return stimulus(), heccalc_inst, heccalc_v_inst
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def testPlain(self):
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sim = self.bench(HecCalculatorPlain)
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Simulation(sim).run()
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## def testPlain(self):
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## sim = self.bench(HecCalculatorPlain)
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## Simulation(sim).run()
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def testFunc(self):
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sim = self.bench(HecCalculatorFunc)
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Simulation(sim).run()
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## def testTask(self):
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## sim = self.bench(HecCalculatorTask)
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## Simulation(sim).run()
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