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jand 2003-08-08 17:23:55 +00:00
parent 87e7661895
commit 2b682b8b9c
3 changed files with 17 additions and 8 deletions
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11
doc/manual/cosimulation.tex
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@ -392,9 +392,13 @@ to introduce new, well defined callbacks. From reading some proposals,
I conclude that the \code{cbEndOfSimTime} callback would provide the
required functionality.
I currently have no access to commercial Verilog simulators, so
progress in co-simulation support will depend on external interest and
participation. Contact me for more information if you interested.
\subsection{VHDL \label{cosim-impl-vhdl}}
It would be great to have an interface to VHDL simulators such as the
It would be nice to have an interface to VHDL simulators such as the
Modelsim VHDL simulator. This will require a PLI module using the
PLI of the VHDL simulator. One feature which I would
like to keep if possible is the way to declare the communicating
@ -402,3 +406,8 @@ signals. In the Verilog solution, it is not necessary to define and
instantiate a special HDL module (entity). Rather, the participating
signals can be declared directly in the \code{\$to_myhdl} and
\code{\$from_myhdl} task calls.
As for Verilog, I currently have no access to commercial VHDL
simulators, so progress in co-simulation support will depend on
external interest and participation. Contact me for more information
if you interested.

6
doc/manual/informal.tex
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@ -339,9 +339,9 @@ objects.
As in standard Python, the slicing range is half-open: the highest
index bit is not included. Unlike standard Python however, this index
corresponds to the \emph{leftmost} item. Both indices can be ommitted
from the slice. If the leftmost index is ommitted, the meaning is to
access ``all'' higher order bits. If the rightmost index is ommitted,
corresponds to the \emph{leftmost} item. Both indices can be omitted
from the slice. If the leftmost index is omitted, the meaning is to
access ``all'' higher order bits. If the rightmost index is omitted,
it is \code{0} by default.
The half-openness of a slice may seem awkward at first, but it helps

8
doc/manual/reference.tex
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@ -177,7 +177,7 @@ immediately.
\section{Modelling support\label{ref-misc}}
\section{Modeling support\label{ref-misc}}
\declaremodule{}{myhdl}
\begin{funcdesc}{always_comb}{func}
@ -230,16 +230,16 @@ assigned to a type name. For example:
t_EnumType = enum('ATTR_NAME_1', 'ATTR_NAME_2', ...)
\end{verbatim}
The enumeration type identifiers are available as attributes of
the typename, for example: \code{t_EnumType.ATTR_NAME_1}
the type name, for example: \code{t_EnumType.ATTR_NAME_1}
\end{funcdesc}
\begin{funcdesc}{instances}{}
Looks up all \myhdl\ instances in the local namespace and returns them
Looks up all \myhdl\ instances in the local name space and returns them
in a list.
\end{funcdesc}
\begin{funcdesc}{processes}{}
Looks up all processes in the local namespace, calls each of them,
Looks up all processes in the local name space, calls each of them,
returns the resulting generators in a list. In \myhdl{}, a process is
defined as a local generator function with no parameters.
\end{funcdesc}