Check for "augmented signal assignemnt" (unsupported).

This has no semantic equivalence in Verilog/VHDL

--HG--
branch : 0.6-maint

myhdl/conversion/_analyze.py

@@ -739,7 +739,7 @@ class _AnalyzeVisitor(_ConversionMixin):
             elif access == _access.UNKNOWN:
                 pass
             else: 
-                raise AssertionError
+                self.raiseError(node, _error.NotSupported, "Augmented signal assignment")
         if n in self.ast.vardict:
             obj = self.ast.vardict[n]
             if access == _access.INOUT:

myhdl/test/conversion/general/test_errors.py

@@ -0,0 +1,23 @@
+from myhdl import *
+from myhdl import ConversionError
+from myhdl.conversion._misc import _error
+from myhdl.conversion import verify
+
+
+def sigAugmAssignUnsupported(z, a):
+    @always(a)
+    def logic():
+        z.next += a
+    return logic
+
+def testSigAugmAssignUnsupported():
+    z = Signal(intbv(0)[8:])
+    a = Signal(intbv(0)[8:])
+    try:
+        verify(sigAugmAssignUnsupported, z, a)
+    except ConversionError, e:
+        assert e.kind == _error.NotSupported
+    else:
+        assert False
+
+