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This commit is contained in:
Jan Decaluwe 2014-04-11 15:02:50 +02:00
parent 120537ff0a
commit 2c742c425b
18 changed files with 76 additions and 108 deletions
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16
myhdl/_intbv.py
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@ -98,17 +98,17 @@ class intbv(object):
# copy methods
def __copy__(self):
c = type(self)(self._val)
c._min = self._min
c._max = self._max
c._nrbits = self._nrbits
return c
c._min = self._min
c._max = self._max
c._nrbits = self._nrbits
return c
def __deepcopy__(self, visit):
c = type(self)(self._val)
c._min = self._min
c._max = self._max
c._nrbits = self._nrbits
return c
c._min = self._min
c._max = self._max
c._nrbits = self._nrbits
return c
# iterator method
def __iter__(self):

8
myhdl/conversion/_analyze.py
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@ -532,7 +532,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
self.raiseError(node, _error.ModbvRange, n)
ws = getattr(obj, 'lenStr', False)
ext = getattr(obj, 'external', False)
if ws and ws in self.tree.symdict:
if ws and ws in self.tree.symdict:
_constDict[ws] = self.tree.symdict[ws]
if ext:
_extConstDict[ws] = self.tree.symdict[ws]
@ -827,7 +827,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
node.edge = sig.posedge
ws = getattr(sig._val, 'lenStr', False)
ext = getattr(sig._val, 'external', False)
if ws and ws in self.tree.symdict:
if ws and ws in self.tree.symdict:
_constDict[ws] = self.tree.symdict[ws]
if ext:
_extConstDict[ws] = self.tree.symdict[ws]
@ -869,7 +869,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
self.tree.hasLos = True
ws = getattr(m.elObj._val, 'lenStr', False)
ext = getattr(m.elObj._val, 'external', False)
if ws and ws in self.tree.symdict:
if ws and ws in self.tree.symdict:
_constDict[ws] = self.tree.symdict[ws]
if ext:
_extConstDict[ws] = self.tree.symdict[ws]
@ -884,7 +884,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
# typedef string for nonlocal intbv's
ws = getattr(v, 'lenStr', False)
ext = getattr(v, 'external', False)
if ws and ws in self.tree.symdict:
if ws and ws in self.tree.symdict:
_constDict[ws] = self.tree.symdict[ws]
if ext:
_extConstDict[ws] = self.tree.symdict[ws]

10
myhdl/conversion/_toVHDL.py
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@ -419,8 +419,8 @@ def _getRangeString(s):
elif s._nrbits is not None:
ls = getattr(s, 'lenStr', False)
if ls:
msb = ls + '-1'
else:
msb = ls + '-1'
else:
msb = s._nrbits-1
return "(%s downto 0)" % msb
else:
@ -861,7 +861,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
if isinstance(lhs.value, ast.Name):
sig = self.tree.symdict[lhs.value.id]
if not sig._numeric:
#if not isinstance(rhs, ast.Num):
#if not isinstance(rhs, ast.Num):
convOpen, convClose = "std_logic_vector(", ")"
self.write(' <= ')
self.SigAss = False
@ -1879,7 +1879,7 @@ class vhd_unsigned(vhd_vector):
ls = self.lenStr
if ls:
return "unsigned(%s-1 downto 0)" % ls
else:
else:
return "unsigned(%s downto 0)" % (self.size-1)
else:
return "unsigned"
@ -1890,7 +1890,7 @@ class vhd_signed(vhd_vector):
ls = self.lenStr
if ls:
return "signed(%s-1 downto 0)" % ls
else:
else:
return "signed(%s downto 0)" % (self.size-1)
else:
return "signed"

40
myhdl/test/benchmark/pypystats.dat
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@ -3,39 +3,7 @@ Test: timer
=====
pypy
----
real 64.74
user 64.36
sys 0.19
Test: lfsr24
=====
pypy
----
real 74.72
user 74.27
sys 0.23
Test: randgen
=====
pypy
----
real 62.53
user 62.07
sys 0.27
Test: longdiv
=====
pypy
----
real 69.69
user 69.22
sys 0.26
Test: findmax
=====
pypy
----
real 97.86
user 97.28
sys 0.30
Command exited with non-zero status 1
real 32.51
user 29.72
sys 0.10

6
myhdl/test/benchmark/test_findmax.py
View File

@ -54,7 +54,7 @@ def test_findmax():
@instance
def stimulus():
stopped.next = 0
stopped.next = 0
yield delay(10)
exp = intbv(0)[W:]
val = intbv(0)[W:]
@ -64,14 +64,14 @@ def test_findmax():
exp[:] = 0
for s in range(L):
random_word[:] = glibc_random(random_word)
val[:] = random_word[W:]
val[:] = random_word[W:]
if exp < val:
exp[:] = val
a[s].next = val
yield clock.negedge
assert z == exp
stopped.next = 1
yield delay(10)
yield delay(10)
return dut, clockgen, stimulus

4
myhdl/test/benchmark/test_longdiv.py
View File

@ -36,7 +36,7 @@ def test_longdiv(nrvectors=2**18):
@instance
def stimulus():
stopped.next = 0
stopped.next = 0
yield delay(10)
random_word = intbv(0)[32:]
p = intbv(0)[16:]
@ -71,7 +71,7 @@ def test_longdiv(nrvectors=2**18):
#print d, p, q, quotient
assert quotient == q
stopped.next = 1
yield delay(10)
yield delay(10)
#raise StopSimulation()
return dut, clockgen, stimulus

2
myhdl/test/benchmark/test_randgen.py
View File

@ -26,7 +26,7 @@ def test_randgen():
clock.next = 1
yield delay(10)
clock.next = 0
print random_word
print random_word
return dut, stimulus

2
myhdl/test/benchmark/test_timer.py
View File

@ -45,4 +45,4 @@ def test_timer(timer):
if __name__ == '__main__':
sim = Simulation(test_timer(timer_var))
sim.run()

2
myhdl/test/benchmark/test_timer_array.py
View File

@ -61,4 +61,4 @@ def test_timer_array(timer):
if __name__ == '__main__':
sim = Simulation(test_timer_array(timer_var))
sim.run()

10
myhdl/test/bugs/test_bug_44.py
View File

@ -24,11 +24,11 @@ def tb_stimulus():
# My logic happens on posedge, so I'll perform all checks on negedge.
yield clk.negedge
for x_val in xrange(-2**WIDTH, 2**WIDTH):
#print('x_val={} x.next={}'.format(x_val, x_val % 2**WIDTH))
x.next = x_val % 2**WIDTH
yield clk.negedge
assert y==(x_val+1)%2**WIDTH, 'y={} but expected {}'.format(y, (x_val+1)%2**WIDTH)
assert z==(x_val-1)%2**WIDTH, 'z={} but expected {}'.format(z, (x_val-1)%2**WIDTH)
#print('x_val={} x.next={}'.format(x_val, x_val % 2**WIDTH))
x.next = x_val % 2**WIDTH
yield clk.negedge
assert y==(x_val+1)%2**WIDTH, 'y={} but expected {}'.format(y, (x_val+1)%2**WIDTH)
assert z==(x_val-1)%2**WIDTH, 'z={} but expected {}'.format(z, (x_val-1)%2**WIDTH)
print('OK!')
raise StopSimulation

2
myhdl/test/bugs/test_bug_aj1s.py
View File

@ -11,7 +11,7 @@ def dut():
for i in range(300):
yield delay(10)
print count
if count-1 < 0:
if count-1 < 0:
count.next = 97
else:
count.next = count-1

32
myhdl/test/bugs/test_bug_enum_toVHDL.py
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@ -4,25 +4,25 @@ from myhdl import *
t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE')
def pcie_legacyint_next_state_logic(state_i, next_state_o, next_state_en_o, interrupt_pending_i, interrupt_assert_o):
@always_comb
def sm_output(): # state machine
if state_i==t_state.WAIT_POSEDGE:
interrupt_assert_o.next=0
next_state_en_o .next=interrupt_pending_i
next_state_o .next=t_state.WAIT_NEGEDGE
elif state_i==t_state.WAIT_NEGEDGE:
interrupt_assert_o.next=1
next_state_en_o .next=not interrupt_pending_i
next_state_o .next=t_state.WAIT_POSEDGE
else:
interrupt_assert_o.next=0
next_state_en_o .next=1
next_state_o .next=t_state.WAIT_POSEDGE
return sm_output
@always_comb
def sm_output(): # state machine
if state_i==t_state.WAIT_POSEDGE:
interrupt_assert_o.next=0
next_state_en_o .next=interrupt_pending_i
next_state_o .next=t_state.WAIT_NEGEDGE
elif state_i==t_state.WAIT_NEGEDGE:
interrupt_assert_o.next=1
next_state_en_o .next=not interrupt_pending_i
next_state_o .next=t_state.WAIT_POSEDGE
else:
interrupt_assert_o.next=0
next_state_en_o .next=1
next_state_o .next=t_state.WAIT_POSEDGE
return sm_output
state = Signal(t_state.WAIT_POSEDGE)
next_state = Signal(t_state.WAIT_POSEDGE)
next_state_en = Signal(bool(0)) # Enable transition to next state
next_state_en = Signal(bool(0)) # Enable transition to next state
interrupt_pending = Signal(bool(0))
interrupt_assert = Signal(bool(0))

32
myhdl/test/bugs/test_bug_enum_toVHDL_2.py
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@ -3,25 +3,25 @@ from myhdl import *
t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot')
def pcie_legacyint_next_state_logic(state_i, next_state_o, next_state_en_o, interrupt_pending_i, interrupt_assert_o):
@always_comb
def sm_output(): # state machine
if state_i==t_state.WAIT_POSEDGE:
interrupt_assert_o.next=0
next_state_en_o .next=interrupt_pending_i
next_state_o .next=t_state.WAIT_NEGEDGE
elif state_i==t_state.WAIT_NEGEDGE:
interrupt_assert_o.next=1
next_state_en_o .next=not interrupt_pending_i
next_state_o .next=t_state.WAIT_POSEDGE
else:
interrupt_assert_o.next=0
next_state_en_o .next=1
next_state_o .next=t_state.WAIT_POSEDGE
return sm_output
@always_comb
def sm_output(): # state machine
if state_i==t_state.WAIT_POSEDGE:
interrupt_assert_o.next=0
next_state_en_o .next=interrupt_pending_i
next_state_o .next=t_state.WAIT_NEGEDGE
elif state_i==t_state.WAIT_NEGEDGE:
interrupt_assert_o.next=1
next_state_en_o .next=not interrupt_pending_i
next_state_o .next=t_state.WAIT_POSEDGE
else:
interrupt_assert_o.next=0
next_state_en_o .next=1
next_state_o .next=t_state.WAIT_POSEDGE
return sm_output
state = Signal(t_state.WAIT_POSEDGE)
next_state = Signal(t_state.WAIT_POSEDGE)
next_state_en = Signal(bool(0)) # Enable transition to next state
next_state_en = Signal(bool(0)) # Enable transition to next state
interrupt_pending = Signal(bool(0))
interrupt_assert = Signal(bool(0))

2
myhdl/test/conversion/general/test_adapter.py
View File

@ -26,7 +26,7 @@ def adapter(o_err, i_err, o_spec, i_spec):
@always_comb
def assign():
nomatch.next = 0
nomatch.next = 0
other.next = (other_vec != 0)
o_err.next = o_err_vec

0
myhdl/test/conversion/general/test_intbv_signed.py Executable file → Normal file
View File

10
myhdl/test/conversion/general/test_numass.py
View File

@ -19,31 +19,31 @@ def NumassBench():
r.next = 0
s.next = 0
yield delay(10)
print p, q, r ,s
print p, q, r ,s
p.next = 1
q.next = 1
r.next = 1
s.next = 1
yield delay(10)
print p, q, r ,s
print p, q, r ,s
p.next = 2
q.next = 2
r.next = -2
s.next = -2
yield delay(10)
print p, q, r ,s
print p, q, r ,s
p.next = 255
q.next = 246836311517
r.next = 255
s.next = -246836311517
yield delay(10)
print p, q[40:20], q[20:0], r ,s[41:20], s[20:0]
print p, q[40:20], q[20:0], r ,s[41:20], s[20:0]
p.next = 254
q.next = PBIGINT
r.next = -256
s.next = NBIGINT
yield delay(10)
print p, q[40:20], q[20:0], r ,s[41:20], s[20:0]
print p, q[40:20], q[20:0], r ,s[41:20], s[20:0]
return check

6
myhdl/test/conversion/toVerilog/test_misc.py
View File

@ -19,9 +19,9 @@ def or_gate(a,b,c):
return logic
def my_bundle(p,q):
r = Signal(bool(0))
gen_or = or_gate(p,r,q)
return instances()
r = Signal(bool(0))
gen_or = or_gate(p,r,q)
return instances()
# additional level of hierarchy
def ConstWire2(p, q):

0
myhdl/test/core/test_signed.py Executable file → Normal file
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