FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

fixed indent

Browse Source 
--HG--
branch : 0.8-dev
This commit is contained in:
Christopher Felton 2013-05-10 17:01:50 -05:00
parent ec84444352
commit 2c9ddf1223
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
doc/source/manual/rtl.rst
View File

@ -147,7 +147,7 @@ templates are similar. ::
The above sequential template is the most commonly used when The above sequential template is the most commonly used when
writing MyHDL. The following is also used but the reset condition writing MyHDL. The following is also used but the reset condition
and values are explicitly stated. and values are explicitly stated. ::
def top(<parameters>, clock, ..., reset, ...): def top(<parameters>, clock, ..., reset, ...):
... ...