From 303fa28ed40ef7b759a68cd49e611d59b0075be1 Mon Sep 17 00:00:00 2001
From: Keerthan Jaic <jckeerthan@gmail.com>
Date: Thu, 4 Jul 2013 23:04:28 -0400
Subject: [PATCH] VHDL conversion support.

--HG--
branch : mep107
---
 myhdl/conversion/_toVHDL.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
index 2cd5a993..38720123 100644
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -158,7 +158,8 @@ class _ToVHDLConvertor(object):
         _annotateTypes(genlist)
 
         ### infer interface
-        intf = _analyzeTopFunc(func, *args, **kwargs)
+        top_inst = h.hierarchy[0]
+        intf = _analyzeTopFunc(top_inst, func, *args, **kwargs)
         intf.name = name
         # sanity checks on interface
         for portname in intf.argnames: