diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py
index bad86c26..ef321221 100644
--- a/myhdl/_Signal.py
+++ b/myhdl/_Signal.py
@@ -101,6 +101,10 @@ class Signal(object):
             self._max = val._max
             self._nrbits = val._len
             self._setNextVal = self._setNextIntbv
+            if self._nrbits:
+                self._printVcd = self._printVcdVec
+            else:
+                self._printVcd = self._printVcdHex
         elif val is None:
             self._type = None
             self._setNextVal = self._setNext
diff --git a/myhdl/_traceSignals.py b/myhdl/_traceSignals.py
index 1133ac24..2b8ad509 100644
--- a/myhdl/_traceSignals.py
+++ b/myhdl/_traceSignals.py
@@ -266,7 +266,7 @@ def _writeVcdSigs(f, instances):
                 if w == 1:
                     print >> f, "$var reg 1 %s %s $end" % (s._code, n)
                 else:
-                    print >> f, "$var reg %s %s %s $end" % (w, s.code, n)
+                    print >> f, "$var reg %s %s %s $end" % (w, s._code, n)
             else:
                 print >> f, "$var real 1 %s %s $end" % (s._code, n)
     for i in range(curlevel):