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Merge pull request #157 from jck/mep-114

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Mep 114 update
This commit is contained in:
jandecaluwe 2016-03-15 20:09:14 +01:00
commit 33bf480df6
1 changed files with 38 additions and 4 deletions
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42
myhdl/_block.py
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@ -143,6 +143,7 @@ class _BlockInstance(object):
if hasattr(mod, 'vhdl_code'): if hasattr(mod, 'vhdl_code'):
self.vhdl_code = _UserVhdlCode(mod.vhdl_code, self.symdict, mod.name, self.vhdl_code = _UserVhdlCode(mod.vhdl_code, self.symdict, mod.name,
mod.modfunc, mod.sourcefile, mod.sourceline) mod.modfunc, mod.sourcefile, mod.sourceline)
self._conf_sim = {'trace': False}
def _verifySubs(self): def _verifySubs(self):
for inst in self.subs: for inst in self.subs:
@ -202,15 +203,48 @@ class _BlockInstance(object):
def analyzeConversion(self): def analyzeConversion(self):
return myhdl.conversion.analyze(self) return myhdl.conversion.analyze(self)
def convert(self, hdl='Verilog'): def convert(self, hdl='Verilog', **kwargs):
"""Converts this BlockInstance to another HDL
Args:
hdl (Optional[str]): Target HDL. Defaults to Verilog
path (Optional[str]): Destination folder. Defaults to current
working dir.
name (Optional[str]): Module and output file name. Defaults to
`self.mod.__name__`
trace(Optional[bool]): Verilog only. Whether the testbench should
dump all signal waveforms. Defaults to False.
tb (Optional[bool]): Verilog only. Specifies whether a testbench
should be created. Defaults to True.
timescale(Optional[str]): Verilog only. Defaults to '1ns/10ps'
"""
if hdl.lower() == 'vhdl': if hdl.lower() == 'vhdl':
return myhdl.conversion._toVHDL.toVHDL(self) converter = myhdl.conversion._toVHDL.toVHDL
elif hdl.lower() == 'verilog': elif hdl.lower() == 'verilog':
return myhdl.conversion._toVerilog.toVerilog(self) converter = myhdl.conversion._toVerilog.toVerilog
else: else:
raise BlockInstanceError('unknown hdl %s' % hdl) raise BlockInstanceError('unknown hdl %s' % hdl)
conv_attrs = {}
if 'name' in kwargs:
conv_attrs['name'] = kwargs.pop('name')
conv_attrs['directory'] = kwargs.pop('path', '')
if hdl.lower() == 'verilog':
conv_attrs['no_testbench'] = not kwargs.pop('tb', True)
conv_attrs['timescale'] = kwargs.pop('timescale', '1ns/10ps')
conv_attrs['trace'] = kwargs.pop('trace', False)
conv_attrs.update(kwargs)
for k, v in conv_attrs.items():
setattr(converter, k, v)
return converter(self)
def conf_sim(self, trace=False):
self._conf_sim['trace'] = trace
def run(self, duration=None, quiet=0): def run(self, duration=None, quiet=0):
if self.sim is None: if self.sim is None:
self.sim = myhdl._Simulation.Simulation(self) sim = self
if self._conf_sim['trace']:
sim = myhdl.traceSignals(self)
self.sim = myhdl._Simulation.Simulation(sim)
self.sim.run(duration, quiet) self.sim.run(duration, quiet)