merged always_seq

--HG--
branch : mep107

myhdl/_always_seq.py

@@ -32,6 +32,7 @@ from myhdl._delay import delay
 from myhdl._Signal import _Signal, _WaiterList,_isListOfSigs
 from myhdl._Waiter import _Waiter, _EdgeWaiter, _EdgeTupleWaiter
 from myhdl._instance import _Instantiator
+from myhdl._resolverefs import _AttrRefTransformer
 
 # evacuate this later
 AlwaysSeqError = AlwaysError
@@ -48,14 +49,14 @@ _error.EmbeddedFunction = "embedded functions in always_seq function not support
 class ResetSignal(_Signal):
     def __init__(self, val, active, async):
         """ Construct a ResetSignal.
-        
+
         This is to be used in conjunction with the always_seq decorator,
         as the reset argument.
         """
         _Signal.__init__(self, bool(val))
         self.active = bool(active)
         self.async = async
-  
+
 
 
 def always_seq(edge, reset):
@@ -78,7 +79,7 @@ def always_seq(edge, reset):
             raise AlwaysSeqError(_error.NrOfArgs)
         return _AlwaysSeq(func, edge, reset)
     return _always_seq_decorator
-        
+
 
 class _AlwaysSeq(_Instantiator):
 
@@ -125,7 +126,9 @@ class _AlwaysSeq(_Instantiator):
         s = _dedent(s)
         tree = ast.parse(s)
         # print ast.dump(tree)
-        v = _SigNameVisitor(symdict)
+        v = _AttrRefTransformer(self)
+        v.visit(tree)
+        v = _SigNameVisitor(self.symdict)
         v.visit(tree)
         sigregs = self.sigregs = []
         varregs = self.varregs = []
@@ -139,7 +142,7 @@ class _AlwaysSeq(_Instantiator):
                 assert _isListOfSigs(reg)
                 for e in reg:
                     sigregs.append(e)
-                    
+
 
     def reset_sigs(self):
         for s in self.sigregs:
@@ -223,7 +226,7 @@ class _SigNameVisitor(ast.NodeVisitor):
                 raise AlwaysSeqError(_error.SigAugAssign % id)
             else:
                 raise AssertionError("bug in always_seq")
-            
+
     def visit_Assign(self, node):
         self.context = OUTPUT
         for n in node.targets:
@@ -244,7 +247,7 @@ class _SigNameVisitor(ast.NodeVisitor):
         self.visit(node.target)
         self.context = INPUT
         self.visit(node.value)
-        
+
     def visit_ClassDef(self, node):
         pass # skip
 
@@ -254,8 +257,8 @@ class _SigNameVisitor(ast.NodeVisitor):
     def visit_Print(self, node):
         pass # skip
 
-         
 
 
 
- 
+
+

myhdl/_extractHierarchy.py

@@ -318,16 +318,17 @@ class _HierExtr(object):
                     cellvars = []
                     cellvars.extend(frame.f_code.co_cellvars)
 
-                    local_gens = []
                     #All nested functions will be in co_consts
-                    consts = func.func_code.co_consts
-                    for item in _flatten(arg):
-                        genfunc = _genfunc(item)
-                        if genfunc.func_code in consts:
-                            local_gens.append(item)
-                    if local_gens:
-                        objlist = _resolveRefs(symdict, local_gens)
-                        cellvars.extend(objlist)
+                    if func:
+                        local_gens = []
+                        consts = func.func_code.co_consts
+                        for item in _flatten(arg):
+                            genfunc = _genfunc(item)
+                            if genfunc.func_code in consts:
+                                local_gens.append(item)
+                        if local_gens:
+                            objlist = _resolveRefs(symdict, local_gens)
+                            cellvars.extend(objlist)
                     #for dict in (frame.f_globals, frame.f_locals):
                     for n, v in symdict.items():
                         # extract signals and memories

myhdl/test/conversion/general/test_interfaces.py

@@ -69,7 +69,7 @@ def testbench_two():
     ib = MyIntf()
 
     tb_dut = m_two_level(clock,reset,ia,ib)
-    
+
     @instance
     def tb_clk():
         clock.next = False
@@ -93,7 +93,7 @@ def testbench_two():
         print("%d %d %d %d"%(ia.x,ia.y,ib.x,ib.y))
         raise StopSimulation
 
-    return tb_dut, tb_clk, tb_stim        
+    return tb_dut, tb_clk, tb_stim
 
 def test_one_level_analyze():
     clock = Signal(bool(0))
@@ -111,7 +111,7 @@ def test_two_level_analyze():
     ia = MyIntf()
     ib = MyIntf()
     analyze(m_two_level,clock,reset,ia,ib)
-    
+
 def test_two_level_verify():
     assert verify(testbench_two) == 0