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merged always_seq

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--HG--
branch : mep107
This commit is contained in:
Christopher Felton 2013-07-12 08:42:10 -05:00
commit 3412ad6bc4
3 changed files with 25 additions and 21 deletions
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21
myhdl/_always_seq.py
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@ -32,6 +32,7 @@ from myhdl._delay import delay
from myhdl._Signal import _Signal, _WaiterList,_isListOfSigs from myhdl._Signal import _Signal, _WaiterList,_isListOfSigs
from myhdl._Waiter import _Waiter, _EdgeWaiter, _EdgeTupleWaiter from myhdl._Waiter import _Waiter, _EdgeWaiter, _EdgeTupleWaiter
from myhdl._instance import _Instantiator from myhdl._instance import _Instantiator
from myhdl._resolverefs import _AttrRefTransformer
# evacuate this later # evacuate this later
AlwaysSeqError = AlwaysError AlwaysSeqError = AlwaysError
@ -48,14 +49,14 @@ _error.EmbeddedFunction = "embedded functions in always_seq function not support
class ResetSignal(_Signal): class ResetSignal(_Signal):
def __init__(self, val, active, async): def __init__(self, val, active, async):
""" Construct a ResetSignal. """ Construct a ResetSignal.
This is to be used in conjunction with the always_seq decorator, This is to be used in conjunction with the always_seq decorator,
as the reset argument. as the reset argument.
""" """
_Signal.__init__(self, bool(val)) _Signal.__init__(self, bool(val))
self.active = bool(active) self.active = bool(active)
self.async = async self.async = async
def always_seq(edge, reset): def always_seq(edge, reset):
@ -78,7 +79,7 @@ def always_seq(edge, reset):
raise AlwaysSeqError(_error.NrOfArgs) raise AlwaysSeqError(_error.NrOfArgs)
return _AlwaysSeq(func, edge, reset) return _AlwaysSeq(func, edge, reset)
return _always_seq_decorator return _always_seq_decorator
class _AlwaysSeq(_Instantiator): class _AlwaysSeq(_Instantiator):
@ -125,7 +126,9 @@ class _AlwaysSeq(_Instantiator):
s = _dedent(s) s = _dedent(s)
tree = ast.parse(s) tree = ast.parse(s)
# print ast.dump(tree) # print ast.dump(tree)
v = _SigNameVisitor(symdict) v = _AttrRefTransformer(self)
v.visit(tree)
v = _SigNameVisitor(self.symdict)
v.visit(tree) v.visit(tree)
sigregs = self.sigregs = [] sigregs = self.sigregs = []
varregs = self.varregs = [] varregs = self.varregs = []
@ -139,7 +142,7 @@ class _AlwaysSeq(_Instantiator):
assert _isListOfSigs(reg) assert _isListOfSigs(reg)
for e in reg: for e in reg:
sigregs.append(e) sigregs.append(e)
def reset_sigs(self): def reset_sigs(self):
for s in self.sigregs: for s in self.sigregs:
@ -223,7 +226,7 @@ class _SigNameVisitor(ast.NodeVisitor):
raise AlwaysSeqError(_error.SigAugAssign % id) raise AlwaysSeqError(_error.SigAugAssign % id)
else: else:
raise AssertionError("bug in always_seq") raise AssertionError("bug in always_seq")
def visit_Assign(self, node): def visit_Assign(self, node):
self.context = OUTPUT self.context = OUTPUT
for n in node.targets: for n in node.targets:
@ -244,7 +247,7 @@ class _SigNameVisitor(ast.NodeVisitor):
self.visit(node.target) self.visit(node.target)
self.context = INPUT self.context = INPUT
self.visit(node.value) self.visit(node.value)
def visit_ClassDef(self, node): def visit_ClassDef(self, node):
pass # skip pass # skip
@ -254,8 +257,8 @@ class _SigNameVisitor(ast.NodeVisitor):
def visit_Print(self, node): def visit_Print(self, node):
pass # skip pass # skip

19
myhdl/_extractHierarchy.py
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@ -318,16 +318,17 @@ class _HierExtr(object):
cellvars = [] cellvars = []
cellvars.extend(frame.f_code.co_cellvars) cellvars.extend(frame.f_code.co_cellvars)
local_gens = []
#All nested functions will be in co_consts #All nested functions will be in co_consts
consts = func.func_code.co_consts if func:
for item in _flatten(arg): local_gens = []
genfunc = _genfunc(item) consts = func.func_code.co_consts
if genfunc.func_code in consts: for item in _flatten(arg):
local_gens.append(item) genfunc = _genfunc(item)
if local_gens: if genfunc.func_code in consts:
objlist = _resolveRefs(symdict, local_gens) local_gens.append(item)
cellvars.extend(objlist) if local_gens:
objlist = _resolveRefs(symdict, local_gens)
cellvars.extend(objlist)
#for dict in (frame.f_globals, frame.f_locals): #for dict in (frame.f_globals, frame.f_locals):
for n, v in symdict.items(): for n, v in symdict.items():
# extract signals and memories # extract signals and memories

6
myhdl/test/conversion/general/test_interfaces.py
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@ -69,7 +69,7 @@ def testbench_two():
ib = MyIntf() ib = MyIntf()
tb_dut = m_two_level(clock,reset,ia,ib) tb_dut = m_two_level(clock,reset,ia,ib)
@instance @instance
def tb_clk(): def tb_clk():
clock.next = False clock.next = False
@ -93,7 +93,7 @@ def testbench_two():
print("%d %d %d %d"%(ia.x,ia.y,ib.x,ib.y)) print("%d %d %d %d"%(ia.x,ia.y,ib.x,ib.y))
raise StopSimulation raise StopSimulation
return tb_dut, tb_clk, tb_stim return tb_dut, tb_clk, tb_stim
def test_one_level_analyze(): def test_one_level_analyze():
clock = Signal(bool(0)) clock = Signal(bool(0))
@ -111,7 +111,7 @@ def test_two_level_analyze():
ia = MyIntf() ia = MyIntf()
ib = MyIntf() ib = MyIntf()
analyze(m_two_level,clock,reset,ia,ib) analyze(m_two_level,clock,reset,ia,ib)
def test_two_level_verify(): def test_two_level_verify():
assert verify(testbench_two) == 0 assert verify(testbench_two) == 0