abstract

README.txt

@@ -1,32 +1,45 @@
-MyHDL Release 0.2
+MyHDL Release 0.3
 =================
 
 INTRODUCTION
 ------------
 
 MyHDL is a Python package for using Python as a hardware description
-language. Popular hardware description languages, like Verilog and
+and verification language. Languages such Verilog and VHDL are
-VHDL, are compiled languages. Python with MyHDL can be viewed as a
+compiled languages. Python with MyHDL can be viewed as a "scripting
-"scripting language" counterpart of such languages. However, Python is
+language" counterpart of such languages. However, Python is more
-more accurately described as a very high level language (VHLL). MyHDL
+accurately described as a very high level language (VHLL). MyHDL users
-users have access to the amazing power and elegance of Python for
+have access to the amazing power and elegance of Python.
-their modeling work.
 
-The key idea behind MyHDL is to use Python generators to model the
+The key idea behind MyHDL is to use Python generators for modeling
-concurrency required in hardware descriptions. As generators are a
+hardware concurrency. A generator is a resumable function with
-recent Python feature, MyHDL requires Python 2.2.2 or higher.
+internal state. In MyHDL, a hardware module is modeled as a function
+that returns generators. With this approach, MyHDL directly supports
+features such as named port association, arrays of instances, and
+conditional instantiation.
 
-MyHDL can be used to experiment with high level modeling, and with
+MyHDL supports the classic hardware description concepts. It provides
-verification techniques such as unit testing. The most important
+a signal class similar to the VHDL signal, a class for bit oriented
-practical application however, is to use it as a hardware verification
+operations, and support for enumeration types.  The Python yield
-language by co-simulation with Verilog and VHDL.
+statement is used as a general sensitivity list to wait on a signal
+change, an edge, a delay, or on another generator. MyHDL supports
+waveform viewing by tracing signal changes in a VCD file.
 
-The present release, MyHDL 0.2, enables MyHDL for co-simulation. The
+High level modeling is the ideal application of MyHDL and Python. The
-MyHDL side is designed to work with any simulator that has a PLI. For
+possibilities are extensive and beyond the scope of most other
-each simulator, an appropriate PLI module in C needs to be
+languages. It can be expected that MyHDL users will often have the
-provided. The release contains such a module for the Icarus Verilog
+``Pythonic experience'' of finding an elegant solution to a complex
+modeling problem.
+
+With MyHDL, the Python unit test framework can be used on hardware
+designs.  MyHDL can also be used as hardware verification language for
+VHDL and Verilog designs, by co-simulation with any simulator that has
+a PLI.  The distribution contains a PLI module for the Icarus Verilog
 simulator.
 
+The MyHDL software is open source software. It is licensed under the
+GNU Lesser General Public License (LGPL).
+
 
 INSTALLATION
 ------------

doc/manual/MyHDL.tex

@@ -21,30 +21,51 @@
 
 \noindent
 
-\myhdl\ is a Python package for using Python as a hardware description
+\myhdl{} is a Python package for using Python as a hardware description
-language. Popular hardware description languages, like Verilog and
+and verification language. Languages such Verilog and VHDL are
-VHDL, are compiled languages. Python with \myhdl\ can be viewed as a
+compiled languages. Python with \myhdl{} can be viewed as a "scripting
-"scripting language" counterpart of such languages. However, Python is
+language" counterpart of such languages. However, Python is more
-more accurately described as a very high level language
+accurately described as a very high level language (VHLL). \myhdl{} users
-(VHLL). \myhdl\ users have access to the amazing power and elegance of
+have access to the amazing power and elegance of Python.
-Python for their modeling work.
 
-The key idea behind \myhdl\ is to use Python generators to model the
-concurrency required in hardware descriptions. As generators are a
-recent Python feature, \myhdl\ requires Python 2.2.2 or higher.
 
-\myhdl\ can be used to experiment with high level modeling, and with
+The key idea behind \myhdl{} is to use Python generators for modeling
-verification techniques such as unit testing. The most important
+hardware concurrency. A generator is a resumable function with
-practical application however, is to use it as a hardware verification
+internal state. In \myhdl{}, a hardware module is modeled as a function
-language by co-simulation with Verilog and VHDL.
+that returns generators. With this approach, \myhdl{} directly supports
+features such as named port association, arrays of instances, and
+conditional instantiation. 
 
-The present release, \myhdl\ 0.2, enables \myhdl\ for
+
-co-simulation. The \myhdl\ side is designed to work with any simulator
+\myhdl{} supports the classic hardware description concepts.  It provides
-that has a PLI. For each simulator, an appropriate PLI module in C
+a signal class similar to the VHDL signal, a class for bit oriented
-needs to be provided. The release contains such a module for the
+operations, and support for enumeration types.  The Python
+\code{yield} statement is used as a general sensitivity list to
+wait on a signal change, an edge, a delay, or on another
+generator. \myhdl{} supports waveform viewing by tracing signal changes
+in a VCD file.
+
+
+High level modeling is the ideal application of \myhdl{} and Python.
+The possibilities are extensive and beyond the scope of most other
+languages. It can be expected that \myhdl{} users will often have the
+``Pythonic experience'' of finding an elegant solution to a complex
+modeling problem.
+
+
+With \myhdl{}, the Python unit test framework can be used on hardware
+designs.  \myhdl{} can also be used as hardware verification language for
+VHDL and Verilog designs, by co-simulation with any simulator that has
+a PLI.  The distribution contains a PLI module for the
 Icarus Verilog simulator.
 
 
+The \myhdl{} software is open source software. It is licensed under the
+GNU Lesser General Public License (LGPL).
+
+
+
+
 \end{abstract}
 
 \tableofcontents

doc/manual/modeling.tex

@@ -24,9 +24,9 @@ Note that \myhdl\ uses conventional procedural techniques
 for modeling structure. This makes it straightforward
 to model more complex cases.
 
-\subsection{Conditional generation \label{model-conf}}
+\subsection{Conditional instantiation \label{model-conf}}
 
-To model conditional instance generation, we can
+To model conditional instantiation, we can
 select the returned instance under parameter control.
 For example:
 
@@ -393,7 +393,7 @@ A sync pattern detector continuously looks for a framing
 pattern and indicates it to the FSM with a \code{syncFlag} signal. When
 found, the FSM moves from the initial \code{SEARCH} state to the
 \code{CONFIRM} state. When the \code{syncFlag}
-is confirmed on the expected position, the FSM declares \var{SYNC},
+is confirmed on the expected position, the FSM declares \code{SYNC},
 otherwise it falls back to the \code{SEARCH} state.  This FSM can be
 coded as follows:
 
@@ -551,10 +551,13 @@ only.
 
 \begin{quote}
 \em 
-High level modeling is the true vocation of \myhdl{}.  The
+High level modeling is the ideal application of \myhdl{} and Python.
-possibilities are vast.  This section should be seen as a starting
+The possibilities are extensive and beyond the scope of most other
-point for experiments and exploration. Over time, techniques that
+languages. It can be expected that \myhdl\ users will often have the
-prove useful will be added to this section.
+``Pythonic experience'' of finding an elegant solution to a complex
+modeling problem.  The following section should be seen as a starting
+point for experiments and exploration. Over time, more techniques that
+prove useful will be added.
 \end{quote}
 
 \subsection{Modeling memories with built-in types \label{model-mem}}