packaged myhdl support functions

example/cookbook/sinecomp/SineComputer.py

@@ -106,7 +106,7 @@ def SineComputer(cos_z0, sin_z0, done, z0, start, clock, reset):
 def SineComputer_v(cos_z0, sin_z0, done, z0, start, clock, reset):
     toVerilog(SineComputer, cos_z0, sin_z0, done, z0, start, clock, reset)
     conversion.analyze(SineComputer, cos_z0, sin_z0, done, z0, start, clock, reset)
-    cmd = "cver -q +loadvpi=myhdl_vpi:vpi_compat_bootstrap " + \
+    cmd = "cver -q +loadvpi=./myhdl_vpi:vpi_compat_bootstrap " + \
           "SineComputer.v tb_SineComputer.v"
     return Cosimulation(cmd, **locals())
 ##     cmd = "iverilog SineComputer.v tb_SineComputer.v"

myhdl/__init__.py

@@ -48,7 +48,7 @@ __author__ = "Jan Decaluwe <jan@jandecaluwe.com>"
 __revision__ = "$Revision$"
 __date__ = "$Date$"
 
-__version__ = "0.6dev3"
+__version__ = "0.6dev4"
 
 import sys
 import warnings

myhdl/conversion/_toVHDL.py

@@ -52,8 +52,9 @@ from myhdl.conversion._misc import (_error, _access, _kind,_context,
 from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFunc,
                                        _Ram, _Rom)
 from myhdl._Signal import _WaiterList
-from myhdl.conversion._toVHDLPackage import package
-            
+from myhdl.conversion._toVHDLPackage import _package
+
+_version = myhdl.__version__.replace('.','')
 _converting = 0
 _profileFunc = None
 _enumTypeList = []
@@ -108,6 +109,10 @@ class _ToVHDLConvertor(object):
 
         vpath = name + ".vhd"
         vfile = open(vpath, 'w')
+        ppath = "pck_myhdl_%s.vhd" % _version
+        pfile = None
+        if not os.path.isfile(ppath):
+            pfile = open(ppath, 'w')
 
         siglist, memlist = _analyzeSigs(h.hierarchy)
         arglist = _flatten(h.top)
@@ -118,6 +123,11 @@ class _ToVHDLConvertor(object):
         intf = _analyzeTopFunc(func, *args, **kwargs)
         intf.name = name
 
+        if pfile:
+            _writeFileHeader(pfile, ppath)
+            print >> pfile, _package
+            pfile.close()
+
         _writeFileHeader(vfile, vpath)
         _writeModuleHeader(vfile, intf)
         _writeFuncDecls(vfile)
@@ -155,6 +165,8 @@ def _writeModuleHeader(f, intf):
     print >> f, "use IEEE.numeric_std.all;"
     print >> f, "use std.textio.all;"
     print >> f
+    print >> f, "use work.pck_myhdl_%s.all;" % _version
+    print >> f
     print >> f, "entity %s is" % intf.name
     if intf.argnames:
         f.write("    port (")
@@ -182,7 +194,8 @@ def _writeModuleHeader(f, intf):
 
 
 def _writeFuncDecls(f):
-    print >> f, package
+    return
+    # print >> f, package
 
 
 constwires = []

myhdl/conversion/_toVHDLPackage.py

@@ -17,90 +17,130 @@
 #  License along with this library; if not, write to the Free Software
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
+import myhdl
 
-package = """\
-function to_std_logic (arg: boolean) return std_logic is
-begin
-    if arg then
-        return '1';
-    else
-        return '0';
-    end if;
-end function to_std_logic;
+_version = myhdl.__version__.replace('.','')
 
-function to_unsigned (arg: boolean; size: natural) return unsigned is
-    variable res: unsigned(size-1 downto 0) := (others => '0');
-begin
-    if arg then
-        res(0):= '1';
-    end if;
-    return res;
-end function to_unsigned;
+_package = """\
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
-function to_signed (arg: boolean; size: natural) return signed is
-    variable res: signed(size-1 downto 0) := (others => '0');
-begin
-    if arg then
-        res(0) := '1';
-    end if;
-    return res; 
-end function to_signed;
+package pck_myhdl_%(version)s is
 
-function to_integer(arg: boolean) return integer is
-begin
-    if arg then
-        return 1;
-    else
-        return 0;
-    end if;
-end function to_integer;
+    function to_std_logic (arg: boolean) return std_logic;
 
-function to_integer(arg: std_logic) return integer is
-begin
-    if arg = '1' then
-        return 1;
-    else
-        return 0;
-    end if;
-end function to_integer;
+    function to_unsigned (arg: boolean; size: natural) return unsigned;
 
-function to_unsigned (arg: std_logic; size: natural) return unsigned is
-    variable res: unsigned(size-1 downto 0) := (others => '0');
-begin
-    res(0):= arg;
-    return res;
-end function to_unsigned;
+    function to_signed (arg: boolean; size: natural) return signed;
 
-function to_signed (arg: std_logic; size: natural) return signed is
-    variable res: signed(size-1 downto 0) := (others => '0');
-begin
-    res(0) := arg;
-    return res; 
-end function to_signed;
+    function to_integer(arg: boolean) return integer;
 
-function to_boolean (arg: std_logic) return boolean is
-begin
-    return arg = '1';
-end function to_boolean;
+    function to_integer(arg: std_logic) return integer;
 
-function to_boolean (arg: unsigned) return boolean is
-begin
-    return arg /= 0;
-end function to_boolean;
+    function to_unsigned (arg: std_logic; size: natural) return unsigned;
 
-function to_boolean (arg: signed) return boolean is
-begin
-    return arg /= 0;
-end function to_boolean;
+    function to_signed (arg: std_logic; size: natural) return signed;
 
-function to_boolean (arg: integer) return boolean is
-begin
-    return arg /= 0;
-end function to_boolean;
+    function to_boolean (arg: std_logic) return boolean;
 
-function "-" (arg: unsigned) return signed is
-begin
-    return - signed(resize(arg, arg'length+1));
-end function "-";
+    function to_boolean (arg: unsigned) return boolean;
 
-"""
+    function to_boolean (arg: signed) return boolean;
+
+    function to_boolean (arg: integer) return boolean;
+
+    function "-" (arg: unsigned) return signed;
+
+end pck_myhdl_%(version)s;
+
+
+package body pck_myhdl_%(version)s is
+
+    function to_std_logic (arg: boolean) return std_logic is
+    begin
+        if arg then
+            return '1';
+        else
+            return '0';
+        end if;
+    end function to_std_logic;
+
+    function to_unsigned (arg: boolean; size: natural) return unsigned is
+        variable res: unsigned(size-1 downto 0) := (others => '0');
+    begin
+        if arg then
+            res(0):= '1';
+        end if;
+        return res;
+    end function to_unsigned;
+
+    function to_signed (arg: boolean; size: natural) return signed is
+        variable res: signed(size-1 downto 0) := (others => '0');
+    begin
+        if arg then
+            res(0) := '1';
+        end if;
+        return res; 
+    end function to_signed;
+
+    function to_integer(arg: boolean) return integer is
+    begin
+        if arg then
+            return 1;
+        else
+            return 0;
+        end if;
+    end function to_integer;
+
+    function to_integer(arg: std_logic) return integer is
+    begin
+        if arg = '1' then
+            return 1;
+        else
+            return 0;
+        end if;
+    end function to_integer;
+
+    function to_unsigned (arg: std_logic; size: natural) return unsigned is
+        variable res: unsigned(size-1 downto 0) := (others => '0');
+    begin
+        res(0):= arg;
+        return res;
+    end function to_unsigned;
+
+    function to_signed (arg: std_logic; size: natural) return signed is
+        variable res: signed(size-1 downto 0) := (others => '0');
+    begin
+        res(0) := arg;
+        return res; 
+    end function to_signed;
+
+    function to_boolean (arg: std_logic) return boolean is
+    begin
+        return arg = '1';
+    end function to_boolean;
+
+    function to_boolean (arg: unsigned) return boolean is
+    begin
+        return arg /= 0;
+    end function to_boolean;
+
+    function to_boolean (arg: signed) return boolean is
+    begin
+        return arg /= 0;
+    end function to_boolean;
+
+    function to_boolean (arg: integer) return boolean is
+    begin
+        return arg /= 0;
+    end function to_boolean;
+
+    function "-" (arg: unsigned) return signed is
+    begin
+        return - signed(resize(arg, arg'length+1));
+    end function "-";
+
+end pck_myhdl_%(version)s;
+
+""" % {'version' : _version}

myhdl/conversion/_verify.py

@@ -4,10 +4,12 @@ import tempfile
 import subprocess
 import difflib
 
+import myhdl
 from myhdl._Simulation import Simulation
 from myhdl.conversion._toVHDL import toVHDL
 from myhdl.conversion._toVerilog import toVerilog
 
+_version = myhdl.__version__.replace('.','')
 _simulators = []
 _analyzeCommands = {}
 _elaborateCommands = {}
@@ -30,7 +32,7 @@ def registerSimulator(name=None, analyze=None, elaborate=None, simulate=None):
     _simulateCommands[name] = simulate
 
 registerSimulator(name="GHDL",
-                  analyze="ghdl -a --workdir=work %(topname)s.vhd",
+                  analyze="ghdl -a --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd",
                   elaborate="ghdl -e --workdir=work %(topname)s",
                   simulate="ghdl -r %(topname)s")
 
@@ -48,6 +50,7 @@ class  _VerificationClass(object):
 
         vals = {}
         vals['topname'] = func.func_name
+        vals['version'] = _version
 
         hdl = self.simulator
         if not hdl: