Merge pull request #47 from jck/travis-container

travis: use container based infrastructure

.travis.yml

@@ -1,3 +1,6 @@
+# http://docs.travis-ci.com/user/workers/container-based-infrastructure/
+sudo: false
+
 language: python
 python:
   - "2.6"
@@ -5,15 +8,13 @@ python:
   - "pypy"
   - "3.4"
 
-before_install:
-  - if [ $CI_TARGET == "icarus" ]; then
-      sudo apt-get update -qq;
-      sudo apt-get install -y iverilog;
-    elif [ $CI_TARGET == "ghdl" ]; then
-      sudo apt-add-repository -y ppa:pgavin/ghdl;
-      sudo apt-get update -qq;
-      sudo apt-get install -y ghdl;
-    fi
+addons:
+  apt:
+    sources:
+      - pgavin-ghdl
+    packages:
+      - iverilog
+      - ghdl
 
 install:
   - pip install .
@@ -22,6 +23,7 @@ env:
   - CI_TARGET=core
   - CI_TARGET=icarus
   - CI_TARGET=ghdl
+  - CI_TARGET=bugs
 
 matrix:
   allow_failures:

ci.sh

@@ -31,6 +31,9 @@ elif [ "$CI_TARGET" == "icarus" ]; then
 elif [ "$CI_TARGET" == "ghdl" ]; then
   run_test make -C "myhdl/test/conversion/general" GHDL
   run_test make -C myhdl/test/conversion/toVHDL GHDL
+elif [ "$CI_TARGET" == "bugs" ]; then
+  run_test make -C "myhdl/test/bugs" icarus
+  run_test make -C "myhdl/test/bugs" GHDL
 fi
 
 exit $foundError

cosimulation/modelsim/Makefile

@@ -2,7 +2,7 @@
 WARNS=-Wall
 
 # change this path to point to the pli include files directory for cver
-INCS=-I /opt/Altera/11.0/modelsim_ase/include
+INCS=-I $(shell dirname `which vsim`)/../include
 
 # maybe want -O<something> and/or -g
 

myhdl/_modbv.py

@@ -21,6 +21,7 @@
 from __future__ import absolute_import
 
 from ._intbv import intbv
+from ._compat import long
 
 class modbv(intbv):
     __slots__ = []

myhdl/test/bugs/test_bug_1740778.py

@@ -22,11 +22,11 @@ def bug_1740778 ():
     def logic():
         v = intbv(0, min=-15, max=45)
         yield delay(10)
-        print v.min
-        print v.max
-        print s.val
-        print s.min
-        print s.max
+        print(v.min)
+        print(v.max)
+        print(s.val)
+        print(s.min)
+        print(s.max)
         
     return logic
 

myhdl/test/bugs/test_bug_1835792.py

@@ -21,8 +21,8 @@ def bug_1835792 ():
     def logic():
         v = intbv(0, min=-15, max=45)
         yield delay(10)
-        print v.min;
-        print v.max;
+        print(v.min);
+        print(v.max);
         
     return logic
 

myhdl/test/bugs/test_bug_1835797.py

@@ -22,8 +22,8 @@ def bug_1835797():
         v = intbv(0, min=-15, max=45)
         """Wrongly placed docstring"""
         yield delay(10)
-        print v.min
-        print v.max
+        print(v.min)
+        print(v.max)
         
     return logic
 

myhdl/test/bugs/test_bug_39.py

@@ -22,7 +22,7 @@ def dut():
         d.next = 0
         for i in range(100):
             yield delay(10)
-            print rx
+            print(rx)
             a.next = (a + 37) % 256
             b.next = (b + 67) % 256
             c.next = (c + 97) % 256

myhdl/test/bugs/test_bug_44.py

@@ -24,7 +24,7 @@ def dec():
 def tb_stimulus():
     # My logic happens on posedge, so I'll perform all checks on negedge.
     yield clk.negedge
-    for x_val in xrange(-2**WIDTH, 2**WIDTH):
+    for x_val in range(-2**WIDTH, 2**WIDTH):
         #print('x_val={} x.next={}'.format(x_val, x_val % 2**WIDTH))
         x.next = x_val % 2**WIDTH
         yield clk.negedge
@@ -36,6 +36,6 @@ def tb_stimulus():
 tb = instances()
 
 def test_bug_44():
-    print instances()
+    print(instances())
     Simulation(tb).run()
 

myhdl/test/bugs/test_bug_aj1s.py

@@ -11,7 +11,7 @@ def dut():
         count.next = 50
         for i in range(300):
             yield delay(10)
-            print count
+            print(count)
             if count-1 < 0:
                count.next = 97
             else:

myhdl/test/bugs/test_issue_10_2.py

@@ -34,7 +34,7 @@ def Logic(flags, position):
         yield delay(10)
         conc.next = concat(flags, position)
         yield delay(10)
-        print conc 
+        print(conc) 
     return doit
 
 def test_issue_10_2():