add support for _to*Convertor derived classes

* Final clean-up moved to _cleanup() method
* adding _convert_filter() method

myhdl/conversion/_toVHDL.py

@@ -151,6 +151,8 @@ class _ToVHDLConvertor(object):
         
         needPck = len(_enumTypeSet) > 0
         
+        self._convert_filter(h, intf, siglist, memlist, genlist)
+        
         if pfile:
             _writeFileHeader(pfile, ppath)
             print >> pfile, _package
@@ -170,7 +172,11 @@ class _ToVHDLConvertor(object):
         # tbfile.close()
 
         ### clean-up properly ###
+        self._cleanup(siglist)
+
+        return h.top
         
+    def _cleanup(self, siglist):
         # clean up signal names
         for sig in siglist:
             sig._clear()
@@ -183,8 +189,12 @@ class _ToVHDLConvertor(object):
         self.component_declarations = None
         self.header = ''
         self.no_myhdl_header = False
-
-        return h.top
+        
+        
+    def _convert_filter(self, h, intf, siglist, memlist, genlist):
+        # intended to be a entry point for other uses: 
+        #  code checking, optimizations, etc
+        pass
     
 
 toVHDL = _ToVHDLConvertor()

myhdl/conversion/_toVerilog.py

@@ -144,6 +144,8 @@ class _ToVerilogConvertor(object):
         intf = _analyzeTopFunc(func, *args, **kwargs)
         intf.name = name
         doc = _makeDoc(inspect.getdoc(func))
+        
+        self._convert_filter(h, intf, siglist, memlist, genlist)
 
         _writeFileHeader(vfile, vpath, self.timescale)
         _writeModuleHeader(vfile, intf, doc)
@@ -160,6 +162,12 @@ class _ToVerilogConvertor(object):
             _writeTestBench(tbfile, intf)
             tbfile.close()
 
+        ### clean-up properly ###
+        self._cleanup(siglist)
+        
+        return h.top
+        
+    def _cleanup(self, siglist):
         # clean up signal names
         for sig in siglist:
             sig._clear()
@@ -176,7 +184,11 @@ class _ToVerilogConvertor(object):
         self.no_myhdl_header = False
         self.no_testbench = False
         
-        return h.top
+        
+    def _convert_filter(self, h, intf, siglist, memlist, genlist):
+        # intended to be a entry point for other uses: 
+        #  code checking, optimizations, etc
+        pass
     
 
 toVerilog = _ToVerilogConvertor()