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add support for _to*Convertor derived classes

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* Final clean-up moved to _cleanup() method
* adding _convert_filter() method
This commit is contained in:
Oscar Diaz 2013-04-15 22:09:45 +02:00
parent 538043b6c7
commit 3bafd2fcaa
2 changed files with 25 additions and 3 deletions
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12
myhdl/conversion/_toVHDL.py
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@ -151,6 +151,8 @@ class _ToVHDLConvertor(object):
needPck = len(_enumTypeSet) > 0 needPck = len(_enumTypeSet) > 0
self._convert_filter(h, intf, siglist, memlist, genlist)
if pfile: if pfile:
_writeFileHeader(pfile, ppath) _writeFileHeader(pfile, ppath)
print >> pfile, _package print >> pfile, _package
@ -170,7 +172,11 @@ class _ToVHDLConvertor(object):
# tbfile.close() # tbfile.close()
### clean-up properly ### ### clean-up properly ###
self._cleanup(siglist)
return h.top
def _cleanup(self, siglist):
# clean up signal names # clean up signal names
for sig in siglist: for sig in siglist:
sig._clear() sig._clear()
@ -184,7 +190,11 @@ class _ToVHDLConvertor(object):
self.header = '' self.header = ''
self.no_myhdl_header = False self.no_myhdl_header = False
return h.top
def _convert_filter(self, h, intf, siglist, memlist, genlist):
# intended to be a entry point for other uses:
# code checking, optimizations, etc
pass
toVHDL = _ToVHDLConvertor() toVHDL = _ToVHDLConvertor()

14
myhdl/conversion/_toVerilog.py
View File

@ -145,6 +145,8 @@ class _ToVerilogConvertor(object):
intf.name = name intf.name = name
doc = _makeDoc(inspect.getdoc(func)) doc = _makeDoc(inspect.getdoc(func))
self._convert_filter(h, intf, siglist, memlist, genlist)
_writeFileHeader(vfile, vpath, self.timescale) _writeFileHeader(vfile, vpath, self.timescale)
_writeModuleHeader(vfile, intf, doc) _writeModuleHeader(vfile, intf, doc)
_writeSigDecls(vfile, intf, siglist, memlist) _writeSigDecls(vfile, intf, siglist, memlist)
@ -160,6 +162,12 @@ class _ToVerilogConvertor(object):
_writeTestBench(tbfile, intf) _writeTestBench(tbfile, intf)
tbfile.close() tbfile.close()
### clean-up properly ###
self._cleanup(siglist)
return h.top
def _cleanup(self, siglist):
# clean up signal names # clean up signal names
for sig in siglist: for sig in siglist:
sig._clear() sig._clear()
@ -176,7 +184,11 @@ class _ToVerilogConvertor(object):
self.no_myhdl_header = False self.no_myhdl_header = False
self.no_testbench = False self.no_testbench = False
return h.top
def _convert_filter(self, h, intf, siglist, memlist, genlist):
# intended to be a entry point for other uses:
# code checking, optimizations, etc
pass
toVerilog = _ToVerilogConvertor() toVerilog = _ToVerilogConvertor()