From 3cf551cb6558f2124497dd19eedd3b7906790101 Mon Sep 17 00:00:00 2001 From: Jan Decaluwe Date: Sat, 25 Apr 2009 19:49:04 +0200 Subject: [PATCH] Removed decprecated Set module import. On some places, the built-in set type was not yet used --HG-- branch : 0.6-maint --- myhdl/_Simulation.py | 3 +-- myhdl/_always_comb.py | 5 ++--- myhdl/_extractHierarchy.py | 1 - myhdl/_misc.py | 3 +-- myhdl/_traceSignals.py | 1 - myhdl/_util.py | 3 +-- myhdl/conversion/_analyze.py | 11 +++++------ myhdl/conversion/_toVHDL.py | 3 +-- myhdl/conversion/_toVerilog.py | 3 +-- myhdl/test/core/test_always.py | 1 - myhdl/test/core/test_always_comb.py | 17 ++++++++--------- myhdl/test/core/test_instance.py | 1 - 12 files changed, 20 insertions(+), 32 deletions(-) diff --git a/myhdl/_Simulation.py b/myhdl/_Simulation.py index dca6b284..099f6feb 100644 --- a/myhdl/_Simulation.py +++ b/myhdl/_Simulation.py @@ -24,7 +24,6 @@ import sys import os from warnings import warn from types import GeneratorType -from sets import Set from myhdl import Cosimulation, StopSimulation, _SuspendSimulation from myhdl import _simulator, SimulationError @@ -202,7 +201,7 @@ class Simulation(object): def _checkArgs(arglist): waiters = [] - ids = Set() + ids = set() cosim = None for arg in arglist: if isinstance(arg, GeneratorType): diff --git a/myhdl/_always_comb.py b/myhdl/_always_comb.py index c99aa399..935fbfb0 100644 --- a/myhdl/_always_comb.py +++ b/myhdl/_always_comb.py @@ -23,7 +23,6 @@ import sys import inspect from types import FunctionType import compiler -from sets import Set import re from myhdl import Signal, AlwaysCombError @@ -67,8 +66,8 @@ INPUT, OUTPUT, INOUT = range(3) class _SigNameVisitor(object): def __init__(self, symdict): - self.inputs = Set() - self.outputs = Set() + self.inputs = set() + self.outputs = set() self.toplevel = 1 self.symdict = symdict diff --git a/myhdl/_extractHierarchy.py b/myhdl/_extractHierarchy.py index b373bf45..3af41929 100644 --- a/myhdl/_extractHierarchy.py +++ b/myhdl/_extractHierarchy.py @@ -31,7 +31,6 @@ from types import GeneratorType import compiler from compiler import ast import linecache -from sets import Set from myhdl import ExtractHierarchyError, ToVerilogError, ToVHDLError from myhdl._Signal import Signal, _isListOfSigs diff --git a/myhdl/_misc.py b/myhdl/_misc.py index 4133229d..ebd86f8e 100644 --- a/myhdl/_misc.py +++ b/myhdl/_misc.py @@ -30,7 +30,6 @@ import sys import inspect from types import GeneratorType -from sets import Set from types import GeneratorType, ListType, TupleType from myhdl._Cosimulation import Cosimulation @@ -39,7 +38,7 @@ from myhdl._instance import _Instantiator def _isGenSeq(obj): if isinstance(obj, (Cosimulation, _Instantiator)): return True - if not isinstance(obj, (ListType, TupleType, Set)): + if not isinstance(obj, (ListType, TupleType, set)): return False ## if not obj: ## return False diff --git a/myhdl/_traceSignals.py b/myhdl/_traceSignals.py index 5493fe1e..59ba2ee7 100644 --- a/myhdl/_traceSignals.py +++ b/myhdl/_traceSignals.py @@ -28,7 +28,6 @@ import time import os path = os.path import shutil -from sets import Set from myhdl import _simulator, Signal, __version__ from myhdl._extractHierarchy import _HierExtr diff --git a/myhdl/_util.py b/myhdl/_util.py index 3c902030..dcf8d4ed 100644 --- a/myhdl/_util.py +++ b/myhdl/_util.py @@ -26,7 +26,6 @@ import exceptions import sys import inspect import re -from sets import Set from types import FunctionType, GeneratorType, ListType, TupleType import compiler # hope this will always work ... @@ -49,7 +48,7 @@ def _isGenFunc(obj): def _flatten(*args): arglist = [] for arg in args: - if isinstance(arg, (list, tuple, Set)): + if isinstance(arg, (list, tuple, set)): for item in arg: arglist.extend(_flatten(item)) else: diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py index fcd98bbc..6cebb657 100644 --- a/myhdl/conversion/_analyze.py +++ b/myhdl/conversion/_analyze.py @@ -25,7 +25,6 @@ import inspect import compiler from compiler import ast as astNode -from sets import Set from types import GeneratorType, FunctionType, ClassType, MethodType from cStringIO import StringIO import re @@ -302,7 +301,7 @@ def hasType(obj, theType): class ReferenceStack(list): def push(self): - self.append(Set()) + self.append(set()) def add(self, item): self[-1].add(item) def __contains__(self, item): @@ -355,8 +354,8 @@ class _AnalyzeVisitor(_ConversionMixin): def __init__(self, ast): ast.sigdict = {} ast.vardict = {} - ast.inputs = Set() - ast.outputs = Set() + ast.inputs = set() + ast.outputs = set() ast.argnames = [] ast.kind = None ast.hasYield = 0 @@ -365,7 +364,7 @@ class _AnalyzeVisitor(_ConversionMixin): self.ast = ast self.labelStack = [] self.refStack = ReferenceStack() - self.globalRefs = Set() + self.globalRefs = set() def binaryOp(self, node, *args): @@ -684,7 +683,7 @@ class _AnalyzeVisitor(_ConversionMixin): # don't infer a case if there's no elsif test if not node.tests[1:]: return - choices = Set() + choices = set() choices.add(item1._index) for test, suite in node.tests[1:]: if not hasattr(test, 'case'): diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 4fd433d0..071d67f9 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -30,7 +30,6 @@ import inspect from datetime import datetime import compiler from compiler import ast as astNode -from sets import Set from types import GeneratorType, FunctionType, ClassType, StringType from cStringIO import StringIO import __builtin__ @@ -68,7 +67,7 @@ def _flatten(*args): for arg in args: if id(arg) in _userCodeMap['vhdl']: arglist.append(_userCodeMap['vhdl'][id(arg)]) - elif isinstance(arg, (list, tuple, Set)): + elif isinstance(arg, (list, tuple, set)): for item in arg: arglist.extend(_flatten(item)) else: diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index 96855b3a..05118367 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -30,7 +30,6 @@ import inspect from datetime import datetime import compiler from compiler import ast as astNode -from sets import Set from types import GeneratorType, FunctionType, ClassType, TypeType, StringType from cStringIO import StringIO import __builtin__ @@ -63,7 +62,7 @@ def _flatten(*args): for arg in args: if id(arg) in _userCodeMap['verilog']: arglist.append(_userCodeMap['verilog'][id(arg)]) - elif isinstance(arg, (list, tuple, Set)): + elif isinstance(arg, (list, tuple, set)): for item in arg: arglist.extend(_flatten(item)) else: diff --git a/myhdl/test/core/test_always.py b/myhdl/test/core/test_always.py index 18647a5c..415e1352 100644 --- a/myhdl/test/core/test_always.py +++ b/myhdl/test/core/test_always.py @@ -27,7 +27,6 @@ from random import randrange import unittest from unittest import TestCase import inspect -from sets import Set from myhdl import Signal, Simulation, instances, AlwaysError, \ intbv, delay, StopSimulation, now diff --git a/myhdl/test/core/test_always_comb.py b/myhdl/test/core/test_always_comb.py index 0fe5c7dc..1b0034a0 100644 --- a/myhdl/test/core/test_always_comb.py +++ b/myhdl/test/core/test_always_comb.py @@ -27,7 +27,6 @@ from random import randrange import unittest from unittest import TestCase import inspect -from sets import Set from myhdl import Signal, Simulation, instances, AlwaysCombError, \ intbv, delay, StopSimulation, now @@ -92,7 +91,7 @@ class AlwaysCombCompilationTest(TestCase): v = u g = always_comb(h).gen i = g.gi_frame.f_locals['self'] - expected = Set(['a']) + expected = set(['a']) self.assertEqual(i.inputs, expected) def testInfer2(self): @@ -103,7 +102,7 @@ class AlwaysCombCompilationTest(TestCase): g = a g = always_comb(h).gen i = g.gi_frame.f_locals['self'] - expected = Set(['a', 'x']) + expected = set(['a', 'x']) self.assertEqual(i.inputs, expected) def testInfer3(self): @@ -114,7 +113,7 @@ class AlwaysCombCompilationTest(TestCase): a = 1 g = always_comb(h).gen i = g.gi_frame.f_locals['self'] - expected = Set(['x']) + expected = set(['x']) self.assertEqual(i.inputs, expected) def testInfer4(self): @@ -125,7 +124,7 @@ class AlwaysCombCompilationTest(TestCase): x = 1 g = always_comb(h).gen i = g.gi_frame.f_locals['self'] - expected = Set(['a']) + expected = set(['a']) self.assertEqual(i.inputs, expected) @@ -159,7 +158,7 @@ class AlwaysCombCompilationTest(TestCase): c.next[a:0] = x[b:0] g = always_comb(h).gen i = g.gi_frame.f_locals['self'] - expected = Set(['a', 'b', 'x']) + expected = set(['a', 'b', 'x']) self.assertEqual(i.inputs, expected) def testInfer8(self): @@ -170,7 +169,7 @@ class AlwaysCombCompilationTest(TestCase): c.next[8:1+a+v] = x[4:b*3+u] g = always_comb(h).gen i = g.gi_frame.f_locals['self'] - expected = Set(['a', 'b', 'x']) + expected = set(['a', 'b', 'x']) self.assertEqual(i.inputs, expected) def testInfer9(self): @@ -179,7 +178,7 @@ class AlwaysCombCompilationTest(TestCase): c.next[a-1] = x[b-1] g = always_comb(h).gen i = g.gi_frame.f_locals['self'] - expected = Set(['a', 'b', 'x']) + expected = set(['a', 'b', 'x']) self.assertEqual(i.inputs, expected) def testInfer10(self): @@ -190,7 +189,7 @@ class AlwaysCombCompilationTest(TestCase): c.next = f(a, 2*b, d*x) g = always_comb(h).gen i = g.gi_frame.f_locals['self'] - expected = Set(['a', 'b', 'd', 'x']) + expected = set(['a', 'b', 'd', 'x']) self.assertEqual(i.inputs, expected) def testEmbeddedFunction(self): diff --git a/myhdl/test/core/test_instance.py b/myhdl/test/core/test_instance.py index 9a370aac..4f2b4d32 100644 --- a/myhdl/test/core/test_instance.py +++ b/myhdl/test/core/test_instance.py @@ -27,7 +27,6 @@ from random import randrange import unittest from unittest import TestCase import inspect -from sets import Set from myhdl import Signal, Simulation, instances, InstanceError, \ intbv, delay, StopSimulation, now