FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

typo

Browse Source
This commit is contained in:
jand 2003-05-15 09:38:04 +00:00
parent eb8d0e97f7
commit 3d9366adc0
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
doc/cosimulation.tex
View File

@ -374,7 +374,7 @@ is to use the \code{cbReadOnlySync} callback. This callback runs
after all pending events have been processed. However, it does not
permit to create new events in the current time step. The second half
of the solution is to map \myhdl\ delta cycles onto real Verilog time
steps. Note that fortunatly I had some freedom here because of the
steps. Note that fortunately I had some freedom here because of the
restriction that only passive HDL code can be co-simulated.
I chose to make the time granularity in the Verilog simulator a 1000