FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

supporting python 2.6

Browse Source
This commit is contained in:
srivatsansoft 2016-02-24 21:52:38 +05:30
parent 8f0678bdea
commit 41081e3817
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
myhdl/test/bugs/test_issue_104.py
View File

@ -8,9 +8,9 @@ def test():
@instance
def tbstim():
yield delay(10)
print("{:<8d} ".format(now()))
print("{0:<8d} ".format(now()))
yield delay(1000)
print("{:<8d} ".format(now()))
print("{0:<8d} ".format(now()))
for _ in range(10):
yield delay(1000)