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https://github.com/myhdl/myhdl.git
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Bug fix merge from default
--HG-- branch : 0.9-dev
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commit
4189d9ba95
@ -127,6 +127,16 @@ class _SigNameVisitor(ast.NodeVisitor):
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def visit_Attribute(self, node):
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self.visit(node.value)
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def visit_Call(self, node):
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fn = None
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if isinstance(node.func, ast.Name):
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fn = node.func.id
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if fn == "len":
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pass
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else:
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self.generic_visit(node)
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def visit_Subscript(self, node, access=INPUT):
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self.visit(node.value)
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self.context = INPUT
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@ -590,6 +590,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
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elif f is concat:
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node.obj = self.getVal(node)
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elif f is len:
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self.access = _access.UNKNOWN
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node.obj = int(0) # XXX
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elif f is bool:
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node.obj = bool()
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22
myhdl/test/bugs/test_bug_42.py
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22
myhdl/test/bugs/test_bug_42.py
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@ -0,0 +1,22 @@
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#! /usr/bin/env python
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from myhdl import *
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def module(sigin, sigout):
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# Using @always(sigin) only warns, but using @always_comp breaks.
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# The reason is that len(sigout) is interpreted as sigout being used as
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# an input.
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#@always(sigin)
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@always_comb
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def output():
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sigout.next = sigin[len(sigout):]
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return output
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sigin = Signal(intbv(0)[2:])
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sigout = Signal(intbv(0)[2:])
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def test_bug_42():
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toVHDL(module, sigin, sigout)
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24
myhdl/test/bugs/test_bug_42_2.py
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24
myhdl/test/bugs/test_bug_42_2.py
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@ -0,0 +1,24 @@
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#! /usr/bin/env python
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from myhdl import *
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def module(sigin, sigout):
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# Using @always(sigin) only warns, but using @always_comp breaks.
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# The reason is that len(sigout) is interpreted as sigout being used as
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# an input.
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@always(sigin)
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def output():
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sigout.next = sigin[len(sigout):]
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return output
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sigin = Signal(intbv(0)[2:])
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sigout = Signal(intbv(0)[2:])
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def test_bug_42_2():
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toVHDL(module, sigin, sigout)
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toVHDL(module, sigin, sigout)
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