diff --git a/myhdl/_always_comb.py b/myhdl/_always_comb.py
index b6782bb0..68bdbae0 100644
--- a/myhdl/_always_comb.py
+++ b/myhdl/_always_comb.py
@@ -127,6 +127,16 @@ class _SigNameVisitor(ast.NodeVisitor):
     def visit_Attribute(self, node):
         self.visit(node.value)
 
+    def visit_Call(self, node):
+        fn = None
+        if isinstance(node.func, ast.Name):
+            fn = node.func.id
+        if fn == "len":
+            pass
+        else:
+            self.generic_visit(node)
+            
+
     def visit_Subscript(self, node, access=INPUT):
         self.visit(node.value)
         self.context = INPUT
diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py
index 86fde389..04bf8fe0 100644
--- a/myhdl/conversion/_analyze.py
+++ b/myhdl/conversion/_analyze.py
@@ -590,6 +590,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
         elif f is concat:
             node.obj = self.getVal(node)
         elif f is len:
+            self.access = _access.UNKNOWN
             node.obj = int(0) # XXX
         elif f is bool:
             node.obj = bool()
diff --git a/myhdl/test/bugs/test_bug_42.py b/myhdl/test/bugs/test_bug_42.py
new file mode 100644
index 00000000..bac5b875
--- /dev/null
+++ b/myhdl/test/bugs/test_bug_42.py
@@ -0,0 +1,22 @@
+#! /usr/bin/env python
+
+from myhdl import *
+
+def module(sigin, sigout):
+
+    # Using @always(sigin) only warns, but using @always_comp breaks.
+    # The reason is that len(sigout) is interpreted as sigout being used as
+    # an input.
+    #@always(sigin)
+    @always_comb
+    def output():
+         sigout.next = sigin[len(sigout):]
+
+    return output
+
+sigin = Signal(intbv(0)[2:])
+sigout = Signal(intbv(0)[2:])
+
+def test_bug_42():
+    toVHDL(module, sigin, sigout)
+
diff --git a/myhdl/test/bugs/test_bug_42_2.py b/myhdl/test/bugs/test_bug_42_2.py
new file mode 100644
index 00000000..eee4ba4d
--- /dev/null
+++ b/myhdl/test/bugs/test_bug_42_2.py
@@ -0,0 +1,24 @@
+#! /usr/bin/env python
+
+from myhdl import *
+
+def module(sigin, sigout):
+
+    # Using @always(sigin) only warns, but using @always_comp breaks.
+    # The reason is that len(sigout) is interpreted as sigout being used as
+    # an input.
+    @always(sigin)
+    def output():
+         sigout.next = sigin[len(sigout):]
+
+    return output
+
+sigin = Signal(intbv(0)[2:])
+sigout = Signal(intbv(0)[2:])
+
+def test_bug_42_2():
+    toVHDL(module, sigin, sigout)
+
+toVHDL(module, sigin, sigout)
+
+
diff --git a/setup.py b/setup.py
index 977a8435..292e1ed6 100644
--- a/setup.py
+++ b/setup.py
@@ -32,7 +32,7 @@ Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
 
     
 setup(name="myhdl",
-      version="0.8",
+      version="0.9",
       description="Python as a Hardware Description Language",
       long_description = "See home page.",
       author="Jan Decaluwe",