diff --git a/myhdl/_always.py b/myhdl/_always.py index c64bf38d..1dbe033d 100644 --- a/myhdl/_always.py +++ b/myhdl/_always.py @@ -54,7 +54,7 @@ def always(*args): raise AlwaysError(_error.ArgType) if _isGenFunc(func): raise AlwaysError(_error.ArgType) - if func.func_code.co_argcount > 0: + if func.__code__.co_argcount > 0: raise AlwaysError(_error.NrOfArgs) return _Always(func, args) return _always_decorator diff --git a/myhdl/_always_comb.py b/myhdl/_always_comb.py index 523352cf..3bfbefcf 100644 --- a/myhdl/_always_comb.py +++ b/myhdl/_always_comb.py @@ -48,16 +48,16 @@ def always_comb(func): raise AlwaysCombError(_error.ArgType) if _isGenFunc(func): raise AlwaysCombError(_error.ArgType) - if func.func_code.co_argcount > 0: + if func.__code__.co_argcount > 0: raise AlwaysCombError(_error.NrOfArgs) - varnames = func.func_code.co_varnames + varnames = func.__code__.co_varnames symdict = {} - for n, v in func.func_globals.items(): + for n, v in func.__globals__.items(): if n not in varnames: symdict[n] = v # handle free variables - if func.func_code.co_freevars: - for n, c in zip(func.func_code.co_freevars, func.func_closure): + if func.__code__.co_freevars: + for n, c in zip(func.__code__.co_freevars, func.__closure__): try: obj = _cell_deref(c) symdict[n] = obj diff --git a/myhdl/_always_seq.py b/myhdl/_always_seq.py index 95537db9..bd6f87b7 100644 --- a/myhdl/_always_seq.py +++ b/myhdl/_always_seq.py @@ -76,7 +76,7 @@ def always_seq(edge, reset): raise AlwaysSeqError(_error.ArgType) if _isGenFunc(func): raise AlwaysSeqError(_error.ArgType) - if func.func_code.co_argcount > 0: + if func.__code__.co_argcount > 0: raise AlwaysSeqError(_error.NrOfArgs) return _AlwaysSeq(func, edge, reset) return _always_seq_decorator @@ -107,14 +107,14 @@ class _AlwaysSeq(_Instantiator): # find symdict # similar to always_comb, but in class constructor - varnames = func.func_code.co_varnames + varnames = func.__code__.co_varnames symdict = {} - for n, v in func.func_globals.items(): + for n, v in func.__globals__.items(): if n not in varnames: symdict[n] = v # handle free variables - if func.func_code.co_freevars: - for n, c in zip(func.func_code.co_freevars, func.func_closure): + if func.__code__.co_freevars: + for n, c in zip(func.__code__.co_freevars, func.__closure__): try: obj = _cell_deref(c) symdict[n] = obj diff --git a/myhdl/_extractHierarchy.py b/myhdl/_extractHierarchy.py index 98763a99..1ac7cea4 100644 --- a/myhdl/_extractHierarchy.py +++ b/myhdl/_extractHierarchy.py @@ -321,10 +321,10 @@ class _HierExtr(object): #All nested functions will be in co_consts if func: local_gens = [] - consts = func.func_code.co_consts + consts = func.__code__.co_consts for item in _flatten(arg): genfunc = _genfunc(item) - if genfunc.func_code in consts: + if genfunc.__code__ in consts: local_gens.append(item) if local_gens: objlist = _resolveRefs(symdict, local_gens) diff --git a/myhdl/_instance.py b/myhdl/_instance.py index 16e3cad5..956c4e65 100644 --- a/myhdl/_instance.py +++ b/myhdl/_instance.py @@ -38,7 +38,7 @@ def instance(genFunc): raise InstanceError(_error.ArgType) if not _isGenFunc(genFunc): raise InstanceError(_error.ArgType) - if genFunc.func_code.co_argcount > 0: + if genFunc.__code__.co_argcount > 0: raise InstanceError(_error.NrOfArgs) return _Instantiator(genFunc) diff --git a/myhdl/_traceSignals.py b/myhdl/_traceSignals.py index c8562d62..321ea711 100644 --- a/myhdl/_traceSignals.py +++ b/myhdl/_traceSignals.py @@ -76,7 +76,7 @@ class _TraceSignalsClass(object): _tracing = 1 try: if self.name is None: - name = dut.func_name + name = dut.__name__ else: name = str(self.name) if name is None: diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py index a86f2752..c050b826 100644 --- a/myhdl/conversion/_analyze.py +++ b/myhdl/conversion/_analyze.py @@ -158,12 +158,12 @@ def _analyzeGens(top, absnames): #print ast.dump(tree) tree.sourcefile = inspect.getsourcefile(f) tree.lineoffset = inspect.getsourcelines(f)[1]-1 - tree.symdict = f.func_globals.copy() + tree.symdict = f.__globals__.copy() tree.callstack = [] # handle free variables tree.nonlocaldict = {} - if f.func_code.co_freevars: - for n, c in zip(f.func_code.co_freevars, f.func_closure): + if f.__code__.co_freevars: + for n, c in zip(f.__code__.co_freevars, f.__closure__): obj = _cell_deref(c) tree.symdict[n] = obj # currently, only intbv as automatic nonlocals (until Python 3.0) @@ -610,15 +610,15 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin): tree.name = _Label(fname) tree.sourcefile = inspect.getsourcefile(f) tree.lineoffset = inspect.getsourcelines(f)[1]-1 - tree.symdict = f.func_globals.copy() + tree.symdict = f.__globals__.copy() tree.nonlocaldict = {} if fname in self.tree.callstack: self.raiseError(node, _error.NotSupported, "Recursive call") tree.callstack = self.tree.callstack[:] tree.callstack.append(fname) # handle free variables - if f.func_code.co_freevars: - for n, c in zip(f.func_code.co_freevars, f.func_closure): + if f.__code__.co_freevars: + for n, c in zip(f.__code__.co_freevars, f.__closure__): obj = _cell_deref(c) if not isinstance(obj, (int, long, _Signal)): self.raiseError(node, _error.FreeVarTypeError, n) diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 9d0e9f74..3fddfe45 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -127,7 +127,7 @@ class _ToVHDLConvertor(object): _converting = 1 if self.name is None: - name = func.func_name + name = func.__name__ else: name = str(self.name) try: diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index 27541708..9a65d357 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -123,7 +123,7 @@ class _ToVerilogConvertor(object): _converting = 1 if self.name is None: - name = func.func_name + name = func.__name__ else: name = str(self.name) try: diff --git a/myhdl/conversion/_verify.py b/myhdl/conversion/_verify.py index 605d46e0..36f9713b 100644 --- a/myhdl/conversion/_verify.py +++ b/myhdl/conversion/_verify.py @@ -105,8 +105,8 @@ class _VerificationClass(object): def __call__(self, func, *args, **kwargs): vals = {} - vals['topname'] = func.func_name - vals['unitname'] = func.func_name.lower() + vals['topname'] = func.__name__ + vals['unitname'] = func.__name__.lower() vals['version'] = _version hdlsim = self.simulator diff --git a/myhdl/test/conversion/toVerilog/test_GrayInc.py b/myhdl/test/conversion/toVerilog/test_GrayInc.py index 919e91f6..536c8593 100644 --- a/myhdl/test/conversion/toVerilog/test_GrayInc.py +++ b/myhdl/test/conversion/toVerilog/test_GrayInc.py @@ -76,7 +76,7 @@ class TestGrayInc(unittest.TestCase): def bench(self): gray_inc_reg_1 = toVerilog(GrayIncReg, graycnt, enable, clock, reset, width) - gray_inc_reg_v = GrayIncReg_v(GrayIncReg.func_name, graycnt_v, enable, clock, reset, width) + gray_inc_reg_v = GrayIncReg_v(GrayIncReg.__name__, graycnt_v, enable, clock, reset, width) clk_1 = self.clockGen() st_1 = self.stimulus() ch_1 = self.check() diff --git a/myhdl/test/conversion/toVerilog/test_RandomScrambler.py b/myhdl/test/conversion/toVerilog/test_RandomScrambler.py index cd5ecfa0..7a73f523 100644 --- a/myhdl/test/conversion/toVerilog/test_RandomScrambler.py +++ b/myhdl/test/conversion/toVerilog/test_RandomScrambler.py @@ -124,7 +124,7 @@ class TestRandomScrambler(TestCase): i7, i6, i5, i4, i3, i2, i1, i0 ) # time.sleep(1) - rs_v = RandomScrambler_v(RandomScrambler.func_name, + rs_v = RandomScrambler_v(RandomScrambler.__name__, v7, v6, v5, v4, v3, v2, v1, v0, i7, i6, i5, i4, i3, i2, i1, i0 ) diff --git a/myhdl/test/conversion/toVerilog/test_always_comb.py b/myhdl/test/conversion/toVerilog/test_always_comb.py index d391e1f3..848e05a8 100644 --- a/myhdl/test/conversion/toVerilog/test_always_comb.py +++ b/myhdl/test/conversion/toVerilog/test_always_comb.py @@ -98,7 +98,7 @@ class AlwaysCombSimulationTest(TestCase): random.shuffle(vectors) design_inst = toVerilog(design, a, b, c, d, p, q, r) - design_v_inst = design_v(design.func_name, a, b, c, d, p_v, q_v, r_v) + design_v_inst = design_v(design.__name__, a, b, c, d, p_v, q_v, r_v) def clkGen(): while 1: diff --git a/myhdl/test/conversion/toVerilog/test_beh.py b/myhdl/test/conversion/toVerilog/test_beh.py index 7ba46dce..bc17b83d 100644 --- a/myhdl/test/conversion/toVerilog/test_beh.py +++ b/myhdl/test/conversion/toVerilog/test_beh.py @@ -83,7 +83,7 @@ class TestBeh(TestCase): beh_inst = toVerilog(beh, count, enable, clock, reset, n=n) # beh_inst = beh(count, enable, clock, reset, n=n) - beh_inst_v = beh_v(beh.func_name, count_v, enable, clock, reset) + beh_inst_v = beh_v(beh.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) diff --git a/myhdl/test/conversion/toVerilog/test_bin2gray.py b/myhdl/test/conversion/toVerilog/test_bin2gray.py index f113aae5..d85ce15f 100644 --- a/myhdl/test/conversion/toVerilog/test_bin2gray.py +++ b/myhdl/test/conversion/toVerilog/test_bin2gray.py @@ -70,7 +70,7 @@ class TestBin2Gray(TestCase): bin2gray_inst = toVerilog(bin2gray, B, G, width) # bin2gray_inst = bin2gray(B, G, width) - bin2gray_v_inst = bin2gray_v(bin2gray.func_name, B, G_v) + bin2gray_v_inst = bin2gray_v(bin2gray.__name__, B, G_v) def stimulus(): for i in range(2**width): diff --git a/myhdl/test/conversion/toVerilog/test_bugreports.py b/myhdl/test/conversion/toVerilog/test_bugreports.py index 30d4d7ba..1bacb196 100644 --- a/myhdl/test/conversion/toVerilog/test_bugreports.py +++ b/myhdl/test/conversion/toVerilog/test_bugreports.py @@ -36,7 +36,7 @@ def test(): x,a,b,c,d,e = [Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) for i in range(6)] toVerilog(TestModule, x,a,b,c,d,e) - verilogCompile(TestModule.func_name) + verilogCompile(TestModule.__name__) test() @@ -79,7 +79,7 @@ def test(): x,a,b,c,d,e = [Signal(intbv(0,min=-2**(width-1),max=2**(width-1))) for i in range(6)] toVerilog(TestModule, x,a,b,c,d,e) - verilogCompile(TestModule.func_name) + verilogCompile(TestModule.__name__) test() @@ -111,7 +111,7 @@ def test(): SOF = Signal(bool(0)) toVerilog(top, SOF, clk, reset_n) - verilogCompile(top.func_name) + verilogCompile(top.__name__) test() diff --git a/myhdl/test/conversion/toVerilog/test_custom.py b/myhdl/test/conversion/toVerilog/test_custom.py index 6323daa2..8742f3d4 100644 --- a/myhdl/test/conversion/toVerilog/test_custom.py +++ b/myhdl/test/conversion/toVerilog/test_custom.py @@ -235,7 +235,7 @@ class TestInc(TestCase): inc_inst_ref = incRef(count, enable, clock, reset, n=n) inc_inst = toVerilog(incVer, count, enable, clock, reset, n=n) # inc_inst = inc(count, enable, clock, reset, n=n) - inc_inst_v = inc_v(incVer.func_name, count_v, enable, clock, reset) + inc_inst_v = inc_v(incVer.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) diff --git a/myhdl/test/conversion/toVerilog/test_dec.py b/myhdl/test/conversion/toVerilog/test_dec.py index 7abe3f3a..6032f43f 100644 --- a/myhdl/test/conversion/toVerilog/test_dec.py +++ b/myhdl/test/conversion/toVerilog/test_dec.py @@ -183,7 +183,7 @@ class TestDec(TestCase): dec_inst_ref = decRef(count, enable, clock, reset, n=n) dec_inst = toVerilog(dec, count, enable, clock, reset, n=n) # dec_inst = dec(count, enable, clock, reset, n=n) - dec_inst_v = dec_v(dec.func_name, count_v, enable, clock, reset) + dec_inst_v = dec_v(dec.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) diff --git a/myhdl/test/conversion/toVerilog/test_edge.py b/myhdl/test/conversion/toVerilog/test_edge.py index 053b8ac5..bdd4a0fa 100644 --- a/myhdl/test/conversion/toVerilog/test_edge.py +++ b/myhdl/test/conversion/toVerilog/test_edge.py @@ -101,7 +101,7 @@ class TestEdge(TestCase): self.assertEqual(flag, expected) edge_inst = toVerilog(edge, flag, sig, clock) - edge_inst_v = edge_v(edge.func_name, flag, sig, clock) + edge_inst_v = edge_v(edge.__name__, flag, sig, clock) return clockgen, stimulus, delayline, check, edge_inst_v diff --git a/myhdl/test/conversion/toVerilog/test_fsm.py b/myhdl/test/conversion/toVerilog/test_fsm.py index 893b4ddd..9c954cb1 100644 --- a/myhdl/test/conversion/toVerilog/test_fsm.py +++ b/myhdl/test/conversion/toVerilog/test_fsm.py @@ -174,7 +174,7 @@ class FramerCtrlTest(TestCase): framerctrl_ref_inst = FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State) framerctrl_inst = toVerilog(FramerCtrl, SOF, state, syncFlag, clk, reset_n, t_State) - framerctrl_v_inst = FramerCtrl_v(FramerCtrl.func_name, + framerctrl_v_inst = FramerCtrl_v(FramerCtrl.__name__, SOF_v, state_v, syncFlag, clk, reset_n) def clkgen(): diff --git a/myhdl/test/conversion/toVerilog/test_hec.py b/myhdl/test/conversion/toVerilog/test_hec.py index af899618..eddf2fde 100644 --- a/myhdl/test/conversion/toVerilog/test_hec.py +++ b/myhdl/test/conversion/toVerilog/test_hec.py @@ -145,7 +145,7 @@ class TestHec(unittest.TestCase): heccalc_inst = toVerilog(HecCalculator, hec, header) # heccalc_inst = HecCalculator(hec, header) - heccalc_v_inst = HecCalculator_v(HecCalculator.func_name, hec_v, header) + heccalc_v_inst = HecCalculator_v(HecCalculator.__name__, hec_v, header) def stimulus(): for h in headers: diff --git a/myhdl/test/conversion/toVerilog/test_inc.py b/myhdl/test/conversion/toVerilog/test_inc.py index 8f0e2b6e..516c9eed 100644 --- a/myhdl/test/conversion/toVerilog/test_inc.py +++ b/myhdl/test/conversion/toVerilog/test_inc.py @@ -160,7 +160,7 @@ class TestInc(TestCase): inc_inst_ref = incRef(count, enable, clock, reset, n=n) inc_inst = toVerilog(inc, count, enable, clock, reset, n=n) # inc_inst = inc(count, enable, clock, reset, n=n) - inc_inst_v = inc_v(inc.func_name, count_v, enable, clock, reset) + inc_inst_v = inc_v(inc.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) diff --git a/myhdl/test/conversion/toVerilog/test_inc_initial.py b/myhdl/test/conversion/toVerilog/test_inc_initial.py index c9c729e1..cca2367b 100644 --- a/myhdl/test/conversion/toVerilog/test_inc_initial.py +++ b/myhdl/test/conversion/toVerilog/test_inc_initial.py @@ -88,8 +88,8 @@ class TestInc_initial(TestCase): count_v = Signal(intbv(0)[m:]) enable, clock, reset = [Signal(bool()) for i in range(3)] - inc_initial_1 = toVerilog(top, top.func_name, count, enable, clock, reset, n=n) - inc_initial_v = top(top.func_name, count_v, enable, clock, reset, n=n, arch='verilog') + inc_initial_1 = toVerilog(top, top.__name__, count, enable, clock, reset, n=n) + inc_initial_v = top(top.__name__, count_v, enable, clock, reset, n=n, arch='verilog') clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) diff --git a/myhdl/test/conversion/toVerilog/test_infer.py b/myhdl/test/conversion/toVerilog/test_infer.py index 10f7da66..9eec891d 100644 --- a/myhdl/test/conversion/toVerilog/test_infer.py +++ b/myhdl/test/conversion/toVerilog/test_infer.py @@ -296,7 +296,7 @@ class TestInfer(unittest.TestCase): infertest_inst = toVerilog(Infertest, a, out) # infertest_inst = Infertest(hec, header) - infertest_v_inst = Infertest_v(Infertest.func_name, a, out_v) + infertest_v_inst = Infertest_v(Infertest.__name__, a, out_v) def stimulus(): a.next = 1 diff --git a/myhdl/test/conversion/toVerilog/test_loops.py b/myhdl/test/conversion/toVerilog/test_loops.py index 89e474a7..e88e2eb8 100644 --- a/myhdl/test/conversion/toVerilog/test_loops.py +++ b/myhdl/test/conversion/toVerilog/test_loops.py @@ -266,7 +266,7 @@ class TestLoops(unittest.TestCase): looptest_inst = toVerilog(LoopTest, a, out) # looptest_inst = LoopTest(hec, header) - looptest_v_inst = LoopTest_v(LoopTest.func_name, a, out_v) + looptest_v_inst = LoopTest_v(LoopTest.__name__, a, out_v) def stimulus(): for i in range(100): diff --git a/myhdl/test/conversion/toVerilog/test_misc.py b/myhdl/test/conversion/toVerilog/test_misc.py index b56ff069..a233872f 100644 --- a/myhdl/test/conversion/toVerilog/test_misc.py +++ b/myhdl/test/conversion/toVerilog/test_misc.py @@ -58,7 +58,7 @@ class TestConstWires(unittest.TestCase): q_v = Signal(bool(0)) constwire_inst = toVerilog(ConstWire, p, q) - constwire_v_inst = ConstWire_v(ConstWire.func_name, p, q_v) + constwire_v_inst = ConstWire_v(ConstWire.__name__, p, q_v) def stimulus(): for i in range(100): @@ -83,7 +83,7 @@ class TestConstWires(unittest.TestCase): q_v = Signal(intbv(0)[8:]) constwire_inst = toVerilog(ConstWire, p, q) - constwire_v_inst = ConstWire_v(ConstWire.func_name, p, q_v) + constwire_v_inst = ConstWire_v(ConstWire.__name__, p, q_v) def stimulus(): for i in range(100): @@ -133,7 +133,7 @@ class TestIgnoreCode(unittest.TestCase): ignorecode_inst = toVerilog(adder, a, b, c) # ignorecode_inst = adder(a, b, c) - ignorecode_v_inst = Ignorecode_v(adder.func_name, a, b, c_v) + ignorecode_v_inst = Ignorecode_v(adder.__name__, a, b, c_v) def stimulus(): for i in range(100): diff --git a/myhdl/test/conversion/toVerilog/test_newcustom.py b/myhdl/test/conversion/toVerilog/test_newcustom.py index f84dcbc9..13695fe2 100644 --- a/myhdl/test/conversion/toVerilog/test_newcustom.py +++ b/myhdl/test/conversion/toVerilog/test_newcustom.py @@ -235,7 +235,7 @@ class TestInc(TestCase): inc_inst_ref = incRef(count, enable, clock, reset, n=n) inc_inst = toVerilog(incVer, count, enable, clock, reset, n=n) # inc_inst = inc(count, enable, clock, reset, n=n) - inc_inst_v = inc_v(incVer.func_name, count_v, enable, clock, reset) + inc_inst_v = inc_v(incVer.__name__, count_v, enable, clock, reset) clk_1 = self.clockGen(clock) st_1 = self.stimulus(enable, clock, reset) ch_1 = self.check(count, count_v, enable, clock, reset, n=n) diff --git a/myhdl/test/conversion/toVerilog/test_ops.py b/myhdl/test/conversion/toVerilog/test_ops.py index 8bca0c09..79803ec0 100644 --- a/myhdl/test/conversion/toVerilog/test_ops.py +++ b/myhdl/test/conversion/toVerilog/test_ops.py @@ -147,7 +147,7 @@ class TestBinaryOps(TestCase): And, Or, left, right) - binops_v = binaryOps_v(binaryOps.func_name, + binops_v = binaryOps_v(binaryOps.__name__, Bitand_v, Bitor_v, Bitxor_v, @@ -275,7 +275,7 @@ class TestMultiOps(TestCase): And, Or, argm, argn, argp) - multiops_v = multiOps_v(multiOps.func_name, + multiops_v = multiOps_v(multiOps.__name__, Bitand_v, Bitor_v, Bitxor_v, @@ -372,7 +372,7 @@ class TestUnaryOps(TestCase): UnaryAdd, UnarySub, arg) - unaryops_v = unaryOps_v(unaryOps.func_name, + unaryops_v = unaryOps_v(unaryOps.__name__, Not_v, Invert_v, UnaryAdd_v, @@ -515,7 +515,7 @@ class TestAugmOps(TestCase): Sub, Sum, left, right) - augmops_v = augmOps_v( augmOps.func_name, + augmops_v = augmOps_v( augmOps.__name__, Bitand_v, Bitor_v, Bitxor_v, diff --git a/myhdl/test/conversion/toVerilog/test_ram.py b/myhdl/test/conversion/toVerilog/test_ram.py index 3c356e0d..7bc6fb94 100644 --- a/myhdl/test/conversion/toVerilog/test_ram.py +++ b/myhdl/test/conversion/toVerilog/test_ram.py @@ -116,7 +116,7 @@ class TestMemory(TestCase): # mem_inst = ram(dout, din, addr, we, clk, depth) mem_inst = toVerilog(ram, dout, din, addr, we, clk, depth) - mem_v_inst = ram_v(ram.func_name, dout_v, din, addr, we, clk, depth) + mem_v_inst = ram_v(ram.__name__, dout_v, din, addr, we, clk, depth) def stimulus(): for i in range(depth): diff --git a/myhdl/test/conversion/toVerilog/test_rom.py b/myhdl/test/conversion/toVerilog/test_rom.py index 4c695533..13343f95 100644 --- a/myhdl/test/conversion/toVerilog/test_rom.py +++ b/myhdl/test/conversion/toVerilog/test_rom.py @@ -72,7 +72,7 @@ class TestRom(TestCase): # rom_inst = rom(dout, din, addr, we, clk, depth) rom_inst = toVerilog(rom, dout, addr, clk) - rom_v_inst = rom_v(rom.func_name, dout_v, addr, clk) + rom_v_inst = rom_v(rom.__name__, dout_v, addr, clk) def stimulus(): for i in range(D): diff --git a/myhdl/test/conversion/toVerilog/test_signed.py b/myhdl/test/conversion/toVerilog/test_signed.py index e2ba0f78..e14f73fc 100644 --- a/myhdl/test/conversion/toVerilog/test_signed.py +++ b/myhdl/test/conversion/toVerilog/test_signed.py @@ -151,7 +151,7 @@ class TestBinaryOps(TestCase): And, Or, left, right, bit) - binops_v = binaryOps_v(binaryOps.func_name, + binops_v = binaryOps_v(binaryOps.__name__, ## Bitand_v, ## Bitor_v, ## Bitxor_v, @@ -296,7 +296,7 @@ class TestUnaryOps(TestCase): UnaryAdd, UnarySub, arg) - unaryops_v = unaryOps_v(unaryOps.func_name, + unaryops_v = unaryOps_v(unaryOps.__name__, Not_v, Invert_v, UnaryAdd_v, @@ -449,7 +449,7 @@ class TestAugmOps(TestCase): Sub, Sum, left, right) - augmops_v = augmOps_v( augmOps.func_name, + augmops_v = augmOps_v( augmOps.__name__, ## Bitand_v, ## Bitor_v, ## Bitxor_v, diff --git a/myhdl/test/core/test_traceSignals.py b/myhdl/test/core/test_traceSignals.py index 6f04fbb8..0b8ea0ca 100644 --- a/myhdl/test/core/test_traceSignals.py +++ b/myhdl/test/core/test_traceSignals.py @@ -128,19 +128,19 @@ class TestTraceSigs(TestCase): self.fail() def testHierarchicalTrace1(self): - p = "%s.vcd" % fun.func_name + p = "%s.vcd" % fun.__name__ top() self.assert_(path.exists(p)) def testHierarchicalTrace2(self): - pdut = "%s.vcd" % top.func_name - psub = "%s.vcd" % fun.func_name + pdut = "%s.vcd" % top.__name__ + psub = "%s.vcd" % fun.__name__ dut = traceSignals(top) self.assert_(path.exists(pdut)) self.assert_(not path.exists(psub)) def testBackupOutputFile(self): - p = "%s.vcd" % fun.func_name + p = "%s.vcd" % fun.__name__ dut = traceSignals(fun) Simulation(dut).run(1000, quiet=QUIET) _simulator._tf.close()