0.8 doc improvements

MANIFEST.in

@@ -11,6 +11,16 @@ prune .hg
 prune dist
 prune doc
 prune olddoc
+prune myhdl/old_conversion
+prune myhdl/*/work
+prune myhdl/*/*/work
+prune myhdl/*/*/*/work
+prune myhdl/*/work_vlog
+prune myhdl/*/*/work_vlog
+prune myhdl/*/*/*/work_vlog
+prune myhdl/*/work_vcom
+prune myhdl/*/*/work_vcom
+prune myhdl/*/*/*/work_vcom
 #graft doc/html/manual
 #graft doc/html/icons
 #graft doc/html/whatsnew*

README.txt

@@ -26,13 +26,13 @@ Documentation
 -------------
 The manual is available on-line:
 
-   http://www.myhdl.org/doc/0.7/manual
+   http://www.myhdl.org/doc/0.8/manual
 
 What's new
 ----------
 To find out what's new in this release, please read:
 
-    http://www.myhdl.org/doc/0.7/whatsnew/0.7.html
+    http://www.myhdl.org/doc/0.8/whatsnew/0.8.html
 
 Installation
 ------------

doc/source/manual/conversion.rst

@@ -171,14 +171,14 @@ design.
 Coding style
 ------------
 
-A natural restriction on convertible code is that it should be written in MyHDL
-style: cooperating generators, communicating through signals, and with
-sensitivity specify resume conditions. 
+A natural restriction on convertible code is that it should be written
+in MyHDL style: cooperating generators, communicating through signals,
+and with sensitivity specify resume conditions.
 
 For pure modeling, it doesn't matter how generators are created.
-However, in convertible code they should be created using one
-of the MyHDL decorators: :func:`instance`, :func:`always` or
-:func:`always_comb`.
+However, in convertible code they should be created using one of the
+MyHDL decorators: :func:`instance`, :func:`always`,
+:func:`always_seq`, or :func:`always_comb`.
 
 
 .. _conv-subset-types:

doc/source/manual/rtl.rst

@@ -130,9 +130,8 @@ Template
 --------
 
 Sequential RTL models are sensitive to a clock edge. In addition, they may be
-sensitive to a reset signal. We will describe one of the most common patterns: a
-template with a rising clock edge and an asynchronous reset signal. Other
-templates are similar. ::
+sensitive to a reset signal.  The func:`always_seq` decorator supports this
+model directly::
 
    def top(<parameters>, clock, ..., reset, ...):
        ...
@@ -142,28 +141,21 @@ templates are similar. ::
        ...
        return seqLogic, ...
 
+The :func:`always_seq` decorator is automatically infers the reset
+functionality.  It detects which signals need to be reset, and uses their
+initial values as the reset values. The reset signal itself needs to be
+specified with as a :class:`ResetSignal`, for example::
+
+    reset = ResetSignal(0, active=0, async=True)
+
+The first parameter specifies the initial value. The *active* parameter
+specifies the value on which the reset is active and the *async*
+parameter specifies whether it is an asychronous (`True`) or a
+synchronous (`False`) reset. If no reset is needed, you can assign
+`None` to the *reset* parameter in the func:`always_seq` parameter.
 
 .. _model-seq-ex:
 
-The above sequential template is the most commonly used when
-writing MyHDL.  The following is also used but the reset condition
-and values are explicitly stated. ::
-
-    def top(<parameters>, clock, ..., reset, ...):
-        ...
-        @always(clock.posedge, reset.negedge)
-        def seqLogic():
-           if not reset:
-               <reset code>
-           else:
-               <functional code>
-
-.. _mode-seq-ex2:
-
-In some cases the second form is required but generally the first
-template is concise without loss of generality and the *functional
-code* is more prominent.
-
 Example
 -------
 
@@ -256,6 +248,26 @@ The simulation produces the following output::
       1      2
    StopSimulation
 
+.. _mode-seq-templ-alt:
+
+Alternative template
+--------------------
+
+The template with the func:`always_seq` decorator is convenient
+as it infers the reset functionality automatically. Alternatively,
+you can use a more explicit template as follows::
+
+    def top(<parameters>, clock, ..., reset, ...):
+        ...
+        @always(clock.posedge, reset.negedge)
+        def seqLogic():
+           if not reset:
+               <reset code>
+           else:
+               <functional code>
+
+With this template, the reset values have to be specified
+explicitly.
 
 .. _model-fsm:
 

setup.py

@@ -38,11 +38,10 @@ setup(name="myhdl",
       author="Jan Decaluwe",
       author_email="jan@jandecaluwe.com",
       url="http://www.myhdl.org",
-      download_url="http://sourceforge.net/project/showfiles.php?group_id=91207",
+      download_url="https://bitbucket.org/jandecaluwe/myhdl/get/0.8.zip",
       packages=['myhdl', 'myhdl.conversion'],
       license="LGPL",
       platforms=["Any"],
       keywords="HDL ASIC FPGA hardware design",
       classifiers=filter(None, classifiers.split("\n")),
       )
-