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added check for double underscore in VHDL names

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This commit is contained in:
Josy Boelen 2018-12-05 19:18:42 +01:00
parent 286b699032
commit 43e4190a6a
1 changed files with 3 additions and 0 deletions
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myhdl/conversion/_VHDLNameValidation.py
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@ -41,6 +41,9 @@ def _nameValid(name):
if '-' in name:
warnings.warn("VHDL variable names cannot contain '-': %s" % (name))
if '__' in name:
warnings.warn("VHDL variable names cannot contain double underscores '__': %s" % (name))
if name.lower() in _usedNames:
warnings.warn("Previously used name being reused: %s" % (name))