Added README.txt

example/arith_lib/PrefixAnd.py

@@ -14,7 +14,7 @@ def PrefixAnd(width, speed, PI, PO):
         PT = Signal(intbv())
         while 1:
             yield PI, PT
-            PT.next[n:] = PI.val
+            PT.next[n:] = PI.val[n:]
             for l in range(1, m+1):
                 for k in range(2**(m-l)):
                     for i in range(2**(l-1)):

example/arith_lib/README.txt

@@ -0,0 +1,17 @@
+The examples in this directory are based on VHDL code from the
+"arith_lib" library, Version 1.0, written by Reto Zimmerman, who holds
+the copyright for the original code. The project web page is at
+<http://www.iis.ee.ethz.ch/~zimmi/arith_lib.html>.
+
+I translated a few modules into myhdl/Python and added testbenches to
+verify and demonstrate myhdl modelling, as well as Python's unittest
+framework. The arith_lib library is useful for these purposes as it
+contains a (simple) behavioral architecture as well as a (sometimes
+complex) structural architecture for each module.
+
+The testbenches are the files called test_<Name>.py. Run them as
+follows:
+
+    python test_<Name>.py
+
+