FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity

inout ports

Browse Source
This commit is contained in:
jand 2007-12-12 15:16:29 +00:00
parent 05192b114d
commit 454b2294df
2 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
myhdl/conversion/_toVHDL.py
View File

@ -195,7 +195,9 @@ def _writeModuleHeader(f, intf):
warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
category=ToVHDLWarning
)
f.write("\n %s: out %s%s" % (portname, p, r))
f.write("\n %s: inout %s%s" % (portname, p, r))
else:
f.write("\n %s: out %s%s" % (portname, p, r))
else:
if not s._read:
warnings.warn("%s: %s" % (_error.UnusedPort, portname),

4
myhdl/test/toVHDL/test_fsm.py
View File

@ -201,8 +201,8 @@ def FSMBench(FramerCtrl, t_State):
def testRef():
assert verify(FSMBench, FramerCtrl, t_State_b) == 0
def testAlt():
assert verify(FSMBench, FramerCtrl_alt, t_State_b) == 0
## def testAlt():
## assert verify(FSMBench, FramerCtrl_alt, t_State_b) == 0
## def testRef(self):
## for t_State in (t_State_b, t_State_oc, t_State_oh):