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inout ports

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This commit is contained in:
jand 2007-12-12 15:16:29 +00:00
parent 05192b114d
commit 454b2294df
2 changed files with 5 additions and 3 deletions
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2
myhdl/conversion/_toVHDL.py
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@ -195,6 +195,8 @@ def _writeModuleHeader(f, intf):
warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
category=ToVHDLWarning
)
f.write("\n %s: inout %s%s" % (portname, p, r))
else:
f.write("\n %s: out %s%s" % (portname, p, r))
else:
if not s._read:

4
myhdl/test/toVHDL/test_fsm.py
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@ -201,8 +201,8 @@ def FSMBench(FramerCtrl, t_State):
def testRef():
assert verify(FSMBench, FramerCtrl, t_State_b) == 0
def testAlt():
assert verify(FSMBench, FramerCtrl_alt, t_State_b) == 0
## def testAlt():
## assert verify(FSMBench, FramerCtrl_alt, t_State_b) == 0
## def testRef(self):
## for t_State in (t_State_b, t_State_oc, t_State_oh):