FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity

minor doc fixes

Browse Source
This commit is contained in:
Jan Decaluwe 2008-12-22 18:19:57 +01:00
parent 7255653ed2
commit 46162e8823
4 changed files with 7 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
doc/source/manual/background.rst
View File

@ -38,7 +38,7 @@ A small tutorial on generators
Generators are a relatively recent Python feature. They were introduced in
Python 2.2. Because generators are the key concept in MyHDL, a small tutorial is
included a here.
included here.
Consider the following nonsensical function::

8
doc/source/manual/conversion.rst
View File

@ -558,7 +558,7 @@ For an example of user-defined code, see :ref:`conv-usage-custom`.
Template transformation
=======================
.. note:: This section is only revelant for VHDL.
.. note:: This section is only relevant for VHDL.
There is a difference between VHDL and Verilog in the way in which
sensitivity to signal edges is specified. In Verilog, edge specifiers
@ -631,7 +631,7 @@ VHDL. The convertor will detect those cases and give an error.
Conversion output verification by co-simulation
===============================================
.. note:: This section is only revelant for Verilog.
.. note:: This section is only relevant for Verilog.
To verify the converted Verilog output, co-simulation can be used. To
make this task easier, the converter also generates a test bench that
@ -670,7 +670,7 @@ the :keyword:`raise` statement
A :keyword:`raise` statement can stop the simulation on an error condition.
:func:`delay()` objects
Delay modelling is essential for test benches.
Delay modeling is essential for test benches.
the :keyword:`print` statement
:keyword:`print` statements can be used for simple debugging.
@ -681,7 +681,7 @@ the :keyword:`assert` statement.
self-checking unit tests, controlled by unit test frameworks such as
``py.test``. In particular, they are a powerful way to write
self-checking test benches for MyHDL designs. As :keyword:`assert`
statements are convertible, a whole unittest suite in MyHDL can be
statements are convertible, a whole unit test suite in MyHDL can be
converted to an equivalent test suite in Verilog and VHDL.
Additionally, the same techniques as for synthesizable code can be used

2
doc/source/manual/reference.rst
View File

@ -354,7 +354,7 @@ attributes:
Return the bits as specified by the *_nrbits* attribute of the :class:`intbv`
value as two's complement number when classified as 'unsigned'. The value is
classfied as 'unsigned' if the *min* attribute is >= 0 and *max* > *min*.
classified as 'unsigned' if the *min* attribute is >= 0 and *max* > *min*.
Bit # *_nrbits*-1 specifies then the sign of the value.
:rtype: integer

4
doc/source/whatsnew/0.6.rst
View File

@ -49,7 +49,7 @@ MyHDL as an IP development platform
The possibility to convert the same MyHDL source to equivalent
Verilog and VHDL creates a novel application: using MyHDL as an IP
development platform. IP developers can serve customers for both
target languages from a single MyHDL coe base. Moreover, MyHDL's
target languages from a single MyHDL code base. Moreover, MyHDL's
flexibility and parametrizability make it ideally suited to this
application.
@ -573,8 +573,6 @@ whose valid values are a finite range of positive integers.
This method can be converted to VHDL and Verilog.
.. warning:: Conversion is not yet implemented.
always_comb and list of signals
-------------------------------