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make it work with 2.3

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Added some long casts
put yield for comb logic at the end of function for consistency
This commit is contained in:
jand 2003-06-17 20:27:24 +00:00
parent febac06c8d
commit 464b7c1a67
2 changed files with 10 additions and 7 deletions
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12
myhdl/test_Signal.py
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@ -276,11 +276,11 @@ class TestSignalAsNum(TestCase):
def binaryCheck(self, op, imin=0, imax=None, jmin=0, jmax=None):
self.seqSetup(imin=imin, imax=imax, jmin=jmin, jmax=jmax)
for i, j in zip(self.seqi, self.seqj):
bi = Signal(i)
bj = Signal(j)
ref = op(i, j)
bi = Signal(long(i))
bj = Signal(long(j))
ref = op(long(i), j)
r1 = op(bi, j)
r2 = op(i, bj)
r2 = op(long(i), bj)
r3 = op(bi, bj)
self.assertEqual(type(r1), type(ref))
self.assertEqual(type(r2), type(ref))
@ -293,7 +293,7 @@ class TestSignalAsNum(TestCase):
self.seqSetup(imin=imin, imax=imax, jmin=jmin, jmax=jmax)
for i, j in zip(self.seqi, self.seqj):
bj = Signal(j)
ref = i
ref = long(i)
exec("ref %s j" % op)
r1 = bi1 = Signal(i)
try:
@ -302,7 +302,7 @@ class TestSignalAsNum(TestCase):
pass
else:
self.fail()
r2 = i
r2 = long(i)
exec("r2 %s bj" % op)
r3 = bi3 = Signal(i)
try:

5
myhdl/test_Simulation.py
View File

@ -418,6 +418,8 @@ class DeltaCycleOrder(TestCase):
random.shuffle(vectors)
index = range(4)
f = open("tmp1", "w")
def clkGen():
while 1:
yield delay(10)
@ -439,8 +441,9 @@ class DeltaCycleOrder(TestCase):
def logic():
while 1:
yield a, b, c, d
# yield a, b, c, d
z.next = function(a.val, b.val, c.val, d.val)
yield a, b, c, d
def stimulus():
for v in vectors: