mirror of
https://github.com/myhdl/myhdl.git
synced 2025-01-24 21:52:56 +08:00
vars
This commit is contained in:
jand
parent
970499257d
commit
48b96221c0
@ -26,12 +26,14 @@ __revision__ = "$Revision$"
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__date__ = "$Date$"
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import inspect
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import operator
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import compiler
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from compiler import ast
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from sets import Set
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from types import GeneratorType, ClassType
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from cStringIO import StringIO
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import myhdl
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from myhdl import Signal, intbv
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from myhdl._extractHierarchy import _HierExtr, _findInstanceName
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from myhdl._Error import Error
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@ -100,7 +102,6 @@ def toVerilog(func, *args, **kwargs):
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return h.top
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def _analyzeSigs(hierarchy):
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curlevel = 0
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siglist = []
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@ -147,7 +148,7 @@ def _analyzeGens(top, gennames):
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gen.lineoffset = inspect.getsourcelines(f)[1]-1
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symdict = f.f_globals.copy()
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symdict.update(f.f_locals)
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print f.f_locals
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# print f.f_locals
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sigdict = {}
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for n, v in symdict.items():
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if isinstance(v, Signal):
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@ -158,8 +159,11 @@ def _analyzeGens(top, gennames):
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gen.name = gennames[id(g)]
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else:
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gen.name = genLabel.next()
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v = _AnalyzeGenVisitor(sigdict, gen.sourcefile, gen.lineoffset)
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v = _EvalIntExprVisitor(symdict, gen.sourcefile, gen.lineoffset)
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compiler.walk(gen, v)
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v = _AnalyzeGenVisitor(sigdict, symdict, gen.sourcefile, gen.lineoffset)
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compiler.walk(gen, v)
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gen.vardict = v.vardict
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genlist.append(gen)
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return genlist
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@ -176,33 +180,35 @@ class _ToVerilogMixin(object):
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lineno = lineno or 0
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return lineno
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def raiseError(self, node, kind, msg):
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def raiseError(self, node, kind, msg=""):
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lineno = self.getLineNo(node)
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info = "in file %s, line %s:\n " % \
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(self.sourcefile, self.lineoffset+lineno)
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raise ToVerilogError(kind, msg, info)
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def _require(self, test, msg=""):
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def _require(self, node, test, msg=""):
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if not test:
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self.raiseError(RequirementError, msg, info)
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self.raiseError(node, _error.Requirement, msg)
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class _NotSupportedVisitor(_ToVerilogMixin):
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def visitAssign(self, node, *args):
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if len(node.nodes) > 1:
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self.raiseError(node, _error.NotSupported, "multiple assignments")
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def visitAssList(self, node, *args):
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self.raiseError(node, _error.NotSupported, "list assignment")
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def visitAssTuple(self, node, *args):
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self.raiseError(node, _error.NotSupported, "tuple assignment")
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def visitBackquote(self, node, *args):
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self.raiseError(node, _error.NotSupported, "backquote")
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def visitBreak(self, node, *args):
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self.raiseError(node, _error.NotSupported, "break statement")
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def visitClass(self, node, *args):
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self.raiseError(node, _error.NotSupported, "class statement")
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@ -237,7 +243,7 @@ class _NotSupportedVisitor(_ToVerilogMixin):
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self.raiseError(node, _error.NotSupported, "lambda statement")
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def visitListComp(self, node, *args):
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self.raiseError(node, _error.NotSupported, "list comprehensions")
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self.raiseError(node, _error.NotSupported, "list comprehension")
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def visitList(self, node, *args):
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self.raiseError(node, _error.NotSupported, "list")
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@ -259,19 +265,104 @@ class _NotSupportedVisitor(_ToVerilogMixin):
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def visitUnarySub(self, node, *args):
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self.raiseError(node, _error.NotSupported, "unary subtraction")
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class _EvalIntExprVisitor(_ToVerilogMixin):
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def __init__(self, symdict, sourcefile, lineoffset):
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self.symdict = symdict
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self.sourcefile = sourcefile
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self.lineoffset = lineoffset
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def binaryOp(self, node, op):
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self.visit(node.left)
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self.visit(node.right)
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try:
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node.val = op(node.left.val, node.right.val)
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except:
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node.val = None
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def visitAdd(self, node):
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self.binaryOp(node, operator.add)
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def visitConst(self, node):
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val = node.value
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if isinstance(val, int):
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node.val = val
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else:
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node.val = None
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def visitName(self, node):
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node.val = None
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if node.name in self.symdict:
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val = self.symdict[node.name]
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if isinstance(val, int):
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node.val = val
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INPUT, OUTPUT, INOUT = range(3)
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class _AnalyzeGenVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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def __init__(self, sigdict, sourcefile, lineoffset):
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def __init__(self, sigdict, symdict, sourcefile, lineoffset):
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self.sourcefile = sourcefile
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self.lineoffset = lineoffset
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self.inputs = Set()
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self.outputs = Set()
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self.toplevel = 1
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self.sigdict = sigdict
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self.symdict = symdict
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self.vardict = {}
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def getObj(self, node):
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if hasattr(node, 'obj'):
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return node.obj
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else:
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return None
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def visitAssAttr(self, node, access=OUTPUT):
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self.visit(node.expr, OUTPUT)
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def visitAssign(self, node, access=OUTPUT):
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assert len(node.nodes) == 1
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target, expr = node.nodes[0], node.expr
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self.visit(target, OUTPUT)
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self.visit(expr, INPUT)
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if isinstance(target, ast.AssName):
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n = target.name
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obj = self.getObj(expr)
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if obj is None:
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self.raiseError(node, "cannot infer type")
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self.vardict[n] = obj
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def visitAssName(self, node, *args):
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n = node.name
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self._require(node, n not in self.symdict, "Illegal redeclaration: %s" % n)
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def visitAugAssign(self, node, access=INPUT):
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self.visit(node.node, INOUT)
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self.visit(node.expr, INPUT)
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def visitCallFunc(self, node, *args):
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for child in node.getChildNodes():
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self.visit(child, *args)
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f = self.getObj(node.node)
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# print f
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if type(f) is type and issubclass(f, intbv):
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node.obj = intbv()
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def visitFor(self, node):
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assert isinstance(node.assign, ast.AssName)
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self.visit(node.assign)
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var = node.assign.name
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self.vardict[var] = int()
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self.visit(node.body)
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def visitFunction(self, node):
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if self.toplevel:
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self.toplevel = 0
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print node.code
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self.visit(node.code)
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def visitModule(self, node):
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self.visit(node.node)
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@ -283,48 +374,39 @@ class _AnalyzeGenVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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for n in self.inputs:
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s = self.sigdict[n]
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s._read = True
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def visitFunction(self, node):
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if self.toplevel:
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self.toplevel = 0
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print node.code
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self.visit(node.code)
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def visitName(self, node, access=INPUT):
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n = node.name
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if n not in self.sigdict:
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return
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if access == INPUT:
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self.inputs.add(n)
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elif access == OUTPUT:
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self.outputs.add(n)
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else:
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raise AssertionError
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if n in self.sigdict:
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if access == INPUT:
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self.inputs.add(n)
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elif access == OUTPUT:
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self.outputs.add(n)
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else:
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raise AssertionError
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node.obj = None
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if n in self.vardict:
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node.obj = self.vardict[n]
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if n in self.symdict:
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node.obj = self.symdict[n]
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elif n in __builtins__:
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node.obj = __builtins__[n]
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def visitAssign(self, node, access=OUTPUT):
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for n in node.nodes:
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self.visit(n, OUTPUT)
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self.visit(node.expr, INPUT)
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def visitAssAttr(self, node, access=OUTPUT):
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self.visit(node.expr, OUTPUT)
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def visitSlice(self, node, access=INPUT):
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self.visit(node.expr, access)
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node.obj = self.getObj(node.expr)
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if node.lower:
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self.visit(node.lower, INPUT)
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assert hasattr(node.lower, 'val')
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if isinstance(node.obj, intbv):
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node.obj = intbv()[node.lower.val:]
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if node.upper:
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self.visit(node.upper, INPUT)
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def visitSubscript(self, node, access=INPUT):
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self.visit(node.expr, access)
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for n in node.subs:
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self.visit(n, INPUT)
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def visitSlice(self, node, access=INPUT):
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self.visit(node.expr, access)
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if node.lower:
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self.visit(node.lower, INPUT)
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if node.upper:
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self.visit(node.upper, INPUT)
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def visitAugAssign(self, node, access=INPUT):
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self.visit(node.node, INOUT)
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self.visit(node.expr, INPUT)
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def _analyzeTopFunc(func, *args, **kwargs):
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@ -446,7 +528,6 @@ def _writeTestBench(f, intf):
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print >> f, "endmodule"
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def _getRangeString(s):
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if s._type is bool:
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return ''
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@ -456,35 +537,18 @@ def _getRangeString(s):
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return "[%s:0] " % (s._nrbits-1)
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else:
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raise AssertionError
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class _EvalIntExprVisitor(_ToVerilogMixin):
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def __init__(self, symdict, sourcefile, lineoffset):
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self.symdict = symdict
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self.sourcefile = sourcefile
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self.lineoffset = lineoffset
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def visitAdd(self, node):
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self.visit(node.left)
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self.visit(node.right)
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node.val = node.left.val + node.right.val
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def visitConst(self, node):
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val = node.val = eval(node.value)
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self._require(node, isinstance(val, int), "Expected integer constant")
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def visitName(self, node):
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self._require(node, node.name in self.symdict, \
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"Unresolved symbol %s" % node.name)
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val = node.val = self.symdict[node.name]
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self._require(node, isinstance(val, int), \
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"Expected integer value", node)
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def _convertGens(genlist, vfile):
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for gen in genlist:
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v = _ConvertGenVisitor(vfile, gen.sigdict, gen.symdict, gen.vardict,
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gen.name, gen.sourcefile, gen.lineoffset )
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compiler.walk(gen, v)
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class _ConvertGenVisitor(_ToVerilogMixin):
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def __init__(self, f, sigdict, symdict, name, sourcefile, lineoffset):
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def __init__(self, f, sigdict, symdict, vardict, name, sourcefile, lineoffset):
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self.buf = self.fileBuf = f
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self.name = name
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self.sourcefile = sourcefile
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@ -493,11 +557,12 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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self.codeBuf = StringIO()
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self.sigdict = sigdict
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self.symdict = symdict
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self.vardict = vardict
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# print vardict
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self.ind = ''
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self.inYield = False
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self.isSigAss = False
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self.toplevel = 1
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def write(self, arg):
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self.buf.write("%s" % arg)
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@ -505,6 +570,19 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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def writeline(self):
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self.buf.write("\n%s" % self.ind)
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def writeDeclarations(self):
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for name, obj in self.vardict.items():
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self.writeline()
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if type(obj) is bool:
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self.write("reg %s;" % name)
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elif isinstance(obj, int):
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self.write("integer %s;" % name)
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elif isinstance(obj, intbv):
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self.write("reg [%s-1:0] %s;" % (obj._len, name))
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else:
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raise AssertionError("unexpected type")
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self.writeline()
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def indent(self):
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self.ind += ' ' * 4
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@ -556,9 +634,11 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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self.visit(node.expr)
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self.write(';')
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def visitAssName(self, node):
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# XXX
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pass
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## def visitAssName(self, node):
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## n = node.name
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## assert n in self.vardict
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## if n in self.toDeclare:
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def visitAugAssign(self, node):
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# XXX
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@ -612,13 +692,9 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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self.binaryOp(node, '/')
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def visitFor(self, node):
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print node.lineno
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# print node.lineno
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assert isinstance(node.assign, ast.AssName)
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var = node.assign.name
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print var
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self.buf = self.declBuf
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self.write("integer %s;" % var)
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self.writeline
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self.buf = self.codeBuf
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cf = node.list
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assert isinstance(cf, ast.CallFunc)
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@ -655,12 +731,11 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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self.inYield = False
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self.write(") begin: %s" % self.name)
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self.indent()
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self.writeDeclarations()
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self.buf = self.codeBuf
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for s in w.body.nodes[1:]:
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self.visit(s)
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self.buf = self.fileBuf
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self.writeline()
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self.write(self.declBuf.getvalue())
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self.write(self.codeBuf.getvalue())
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self.dedent()
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self.writeline()
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@ -768,8 +843,20 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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self.binaryOp(node, '>>')
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def visitSlice(self, node):
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# XXX
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pass
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# print dir(node)
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# print node.obj
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self.visit(node.expr)
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self.write("[")
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if node.lower is None:
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self.write("%s" % node.obj._len)
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else:
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self.visit(node.lower)
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self.write("-1:")
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if node.upper is None:
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self.write("0")
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else:
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self.visit(node.upper)
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self.write("]")
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def visitSliceObj(self, node):
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# XXX
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@ -806,14 +893,6 @@ class _ConvertGenVisitor(_ToVerilogMixin):
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self.inYield = False
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def _convertGens(genlist, vfile):
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for gen in genlist:
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print gen.sourcefile
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print gen.lineoffset
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v = _ConvertGenVisitor(vfile, gen.sigdict, gen.symdict, gen.name,
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gen.sourcefile, gen.lineoffset )
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compiler.walk(gen, v)
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@ -12,7 +12,7 @@ def bin2gray(B, G, width):
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G -- output intbv signal, gray encoded
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width -- bit width
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"""
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Bext = intbv(0)[width+1:]
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Bext = intbv(0, max=width)[width+1:]
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while 1:
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yield B
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Bext[:] = B
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