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prefer blocking assignments for combo logic

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(finally giving in :-))
This commit is contained in:
Jan Decaluwe 2010-10-10 21:43:16 +02:00
parent fd05b11e37
commit 4938f11e20
15 changed files with 28 additions and 22 deletions
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2
example/manual/FramerCtrl.v
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@ -1,6 +1,6 @@
// File: FramerCtrl.v
// Generated by MyHDL 0.7dev
// Date: Fri Jul 2 13:23:51 2010
// Date: Sun Oct 10 21:39:53 2010
`timescale 1ns/10ps

3
example/manual/FramerCtrl.vhd
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@ -1,6 +1,7 @@
-- File: FramerCtrl.vhd
-- Generated by MyHDL 0.7dev
-- Date: Fri Jul 2 13:23:51 2010
-- Date: Sun Oct 10 21:39:53 2010
package pck_FramerCtrl is

4
example/manual/GrayIncReg.v
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@ -1,6 +1,6 @@
// File: GrayIncReg.v
// Generated by MyHDL 0.7dev
// Date: Fri Jul 2 13:23:50 2010
// Date: Sun Oct 10 21:39:52 2010
`timescale 1ns/10ps
@ -44,7 +44,7 @@ always @(gray_inc_1_bincnt) begin: GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC
Bext = 9'h0;
Bext = gray_inc_1_bincnt;
for (i=0; i<8; i=i+1) begin
graycnt_comb[i] <= (Bext[(i + 1)] ^ Bext[i]);
graycnt_comb[i] = (Bext[(i + 1)] ^ Bext[i]);
end
end

3
example/manual/GrayIncReg.vhd
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@ -1,6 +1,7 @@
-- File: GrayIncReg.vhd
-- Generated by MyHDL 0.7dev
-- Date: Fri Jul 2 13:23:50 2010
-- Date: Sun Oct 10 21:39:52 2010
library IEEE;
use IEEE.std_logic_1164.all;

2
example/manual/Inc.v
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@ -1,6 +1,6 @@
// File: Inc.v
// Generated by MyHDL 0.7dev
// Date: Fri Jul 2 13:23:50 2010
// Date: Sun Oct 10 21:39:52 2010
`timescale 1ns/10ps

3
example/manual/Inc.vhd
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@ -1,6 +1,7 @@
-- File: Inc.vhd
-- Generated by MyHDL 0.7dev
-- Date: Fri Jul 2 13:23:50 2010
-- Date: Sun Oct 10 21:39:52 2010
library IEEE;
use IEEE.std_logic_1164.all;

4
example/manual/bin2gray.v
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@ -1,6 +1,6 @@
// File: bin2gray.v
// Generated by MyHDL 0.7dev
// Date: Fri Jul 2 13:23:50 2010
// Date: Sun Oct 10 21:39:52 2010
`timescale 1ns/10ps
@ -30,7 +30,7 @@ always @(B) begin: BIN2GRAY_LOGIC
Bext = 9'h0;
Bext = B;
for (i=0; i<8; i=i+1) begin
G[i] <= (Bext[(i + 1)] ^ Bext[i]);
G[i] = (Bext[(i + 1)] ^ Bext[i]);
end
end

3
example/manual/bin2gray.vhd
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@ -1,6 +1,7 @@
-- File: bin2gray.vhd
-- Generated by MyHDL 0.7dev
-- Date: Fri Jul 2 13:23:50 2010
-- Date: Sun Oct 10 21:39:52 2010
library IEEE;
use IEEE.std_logic_1164.all;

2
example/manual/inc_comb.v
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@ -1,6 +1,6 @@
// File: inc_comb.v
// Generated by MyHDL 0.7dev
// Date: Fri Jul 2 13:23:51 2010
// Date: Sun Oct 10 21:39:53 2010
`timescale 1ns/10ps

3
example/manual/inc_comb.vhd
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@ -1,6 +1,7 @@
-- File: inc_comb.vhd
-- Generated by MyHDL 0.7dev
-- Date: Fri Jul 2 13:23:51 2010
-- Date: Sun Oct 10 21:39:53 2010
library IEEE;
use IEEE.std_logic_1164.all;

2
example/manual/ram.vhd
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@ -1,6 +1,6 @@
-- File: ram.vhd
-- Generated by MyHDL 0.7dev
-- Date: Fri Oct 8 21:53:32 2010
-- Date: Sun Oct 10 21:39:53 2010
library IEEE;

2
example/manual/ram_1.v
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@ -1,6 +1,6 @@
// File: ram_1.v
// Generated by MyHDL 0.7dev
// Date: Fri Oct 8 21:53:32 2010
// Date: Sun Oct 10 21:39:53 2010
`timescale 1ns/10ps

10
example/manual/rom.v
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@ -1,6 +1,6 @@
// File: rom.v
// Generated by MyHDL 0.7dev
// Date: Fri Jul 2 13:23:51 2010
// Date: Sun Oct 10 21:39:53 2010
`timescale 1ns/10ps
@ -22,10 +22,10 @@ input [3:0] addr;
always @(addr) begin: ROM_READ
case (addr)
0: dout <= 17;
1: dout <= 134;
2: dout <= 52;
default: dout <= 9;
0: dout = 17;
1: dout = 134;
2: dout = 52;
default: dout = 9;
endcase
end

3
example/manual/rom.vhd
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@ -1,6 +1,7 @@
-- File: rom.vhd
-- Generated by MyHDL 0.7dev
-- Date: Fri Jul 2 13:23:51 2010
-- Date: Sun Oct 10 21:39:53 2010
library IEEE;
use IEEE.std_logic_1164.all;

4
myhdl/conversion/_toVerilog.py
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@ -100,7 +100,7 @@ class _ToVerilogConvertor(object):
self.name = None
self.timescale = "1ns/10ps"
self.standard = '2001'
self.prefer_blocking_assignments = False
self.prefer_blocking_assignments = True
self.radix = ''
self.header = ''
self.no_myhdl_header = False
@ -169,7 +169,7 @@ class _ToVerilogConvertor(object):
# clean up attributes
self.name = None
self.standard = '2001'
self.prefer_blocking_assignments = False
self.prefer_blocking_assignments = True
self.radix = ''
self.header = ""
self.no_myhdl_header = False